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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72324BJ2 датащи(PDF) 33 Page - STMicroelectronics |
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ST72324BJ2 датащи(HTML) 33 Page - STMicroelectronics |
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33 / 188 page  ST72324B Supply, reset and clock management 33/188 The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles then: ● If the AVD interrupt is enabled before the VIT+(AVD) threshold is reached, then 2 AVD interrupts will be received: the first when the AVDIE bit is set, and the second when the threshold is reached. ● If the AVD interrupt is enabled after the VIT+(AVD) threshold is reached then only one AVD interrupt will occur. Figure 17. Using the AVD to monitor VDD 6.5.3 Low power modes 6.5.4 Interrupts The AVD interrupt event generates an interrupt if the AVDIE bit is set and the interrupt mask in the CC register is reset (RIM instruction). M VDD VIT+(AVD) VIT-(AVD) AVDF bit 0 0 Reset value if AVDIE bit = 1 Vhyst AVD Interrupt Request Interrupt process Interrupt process VIT+(LVD) VIT-(LVD) LVD RESET Early warning interrupt (power has dropped, MCU not not yet in reset) 1 1 trv Voltage rise time Table 9. Effect of low power modes on SI Mode Description Wait No effect on SI. AVD interrupt causes the device to exit from Wait mode. Halt The CRSR register is frozen. Table 10. AVD interrupt control/wake-up capability Interrupt event Event flag Enable Control bit Exit from WAIT Exit from HALT AVD event AVDF AVDIE Yes No |
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