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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72324BJ2 датащи(PDF) 43 Page - STMicroelectronics |
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ST72324BJ2 датащи(HTML) 43 Page - STMicroelectronics |
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43 / 188 page  ST72324B Interrupts 43/188 7.6 External interrupts 7.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 22). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt source can be generated on four (or five) different events on the pin: ● Falling edge ● Rising edge ● Falling and rising edge ● Falling edge and low level ● Rising edge and high level (only for ei0 and ei2) To guarantee correct functionality, the sensitivity bits in the EICR register can be modified only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that interrupts must be disabled before changing sensitivity. The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits of the EICR. Figure 22. External interrupt control bits IS10 IS11 EICR PBOR.3 PBDDR.3 IPB BIT PB3 ei2 interrupt source Port B [3:0] interrupts PB3 PB2 PB1 PB0 IS10 IS11 EICR PBOR.4 PBDDR.4 PB4 ei3 interrupt source Port B4 interrupt IS20 IS21 EICR PAOR.3 PADDR.3 IPA BIT PA3 ei0 interrupt source Port A3 interrupt IS20 IS21 EICR PFOR.2 PFDDR.2 PF2 ei1 interrupt source Port F [2:0] interrupts PF2 PF1 PF0 Sensitivity control Sensitivity control Sensitivity Sensitivity control control |
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