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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72324BJ2 датащи(PDF) 75 Page - STMicroelectronics |
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ST72324BJ2 датащи(HTML) 75 Page - STMicroelectronics |
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75 / 188 page  ST72324B On-chip peripherals 75/188 Note: 1 After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2 The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3 The two input capture functions can be used together even if the timer also uses the two output compare functions. 4 In One pulse mode and PWM mode only Input Capture 2 can be used. 5 The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 The TOF bit can be used with interrupt generation in order to measure events that go beyond the timer range (FFFFh). Figure 41. Input capture block diagram Figure 42. Input capture timing diagram ICIE CC0 CC1 16-bit free running counter IEDG1 (Control register 1) CR1 (Control register 2) CR2 ICF2 ICF1 0 0 0 (Status register) SR IEDG2 ICAP1 ICAP2 Edge Detect circuit 2 16-bit IC1R register Edge Detect circuit 1 pin pin IC2R register FF01 FF02 FF03 FF03 Timer clock Counter register ICAPi pin ICAPi flag ICAPi register Note: The rising edge is the active edge. |
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