ST72324BJ2 datasheet(87/188 Pages) STMICROELECTRONICS

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ST72324B

On-chip peripherals

87/188

Input Capture 1 High Register (IC1HR)

This is an 8-bit register that contains the high part of the counter value (transferred by the

input capture 1 event).

6OCF1

Output Compare Flag 1

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC1R

the OC1R (OC1LR) register.

5TOF

Timer Overflow Flag

0: No timer overflow (reset value).

1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first

read the SR register, then read or write the low byte of the CR (CLR) register.

Note: Reading or writing the ACLR register does not clear TOF.

4ICF2

Input Capture Flag 2

0: No input capture (reset value).

1: An Input Capture has occurred on the ICAP2 pin. To clear this bit, first read the SR

3OCF2

Output Compare Flag 2

0: No match (reset value).

1: The content of the free running counter has matched the content of the OC2R

the OC2R (OC2LR) register.

2TIMD

Timer Disable

This bit is set and cleared by software. When set, it freezes the timer prescaler and

counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce

power consumption. Access to the timer registers is still available, allowing the timer

configuration to be changed, or the counter reset, while it is disabled.

0: Timer enabled.

1: Timer prescaler, counter and outputs disabled.

1:0

Reserved, must be kept cleared.

IC1HR

Reset value: undefined

654

MSB

LSB

Table 50.

CSR register description (continued)

Bit

Name

Function

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