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ST72324BJ2 датащи(PDF) 73 Page - STMicroelectronics |
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ST72324BJ2 датащи(HTML) 73 Page - STMicroelectronics |
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73 / 188 page ![]() ST72324B On-chip peripherals 73/188 External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 38. Counter timing diagram, internal clock divided by 2 Figure 39. Counter timing diagram, internal clock divided by 4 Figure 40. Counter timing diagram, internal clock divided by 8 Note: The MCU is in reset state when the internal reset signal is high, when it is low the MCU is running. CPU clock FFFD FFFE FFFF 0000 0001 0002 0003 Internal reset Timer clock Counter register Timer Overflow Flag (TOF) FFFC FFFD 0000 0001 CPU clock Internal reset Timer clock Counter register Timer Overflow Flag (TOF) CPU clock Internal reset Timer clock Counter register Timer Overflow Flag (TOF) FFFC FFFD 0000 |
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