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MPC8XXFADS Design Specification—Rev 0.1

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

RESET_CONFIG_ACTIVE = 0;

"**** changed due to long lock delay of the pda *** 17,7,95 ******************

@ifndef SLOW_PLL_LOCK {

KA_PON_RESET = (RGPORIn == K_A_PON_RESET_ACTIVE);

}

@ifdef SLOW_PLL_LOCK {

PON_DEFAULT_ACTIVE = 0;

KA_PON_RESET = (PonDefault~ == PON_DEFAULT_ACTIVE);

}

"*********** end of change ***************

RESET_CONFIG_DRIVEN = ((ResetConf~ == RESET_CONFIG_ACTIVE) &

(FlashCfgEn~ != FLASH_CFG_ENABLE));

"******************************************************************************

"* Register Access definitions

"******************************************************************************

CONFIG_REG_ADD = 0;

CONTROL_REG_1_ADD = 1;

STATUS_REG2_ADD = 2;

STATUS_REG3_ADD = 3;

CONTROL_REG_4_ADD = 4;

" MPC_WRITE_BCSR_0 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~);

" MPC_WRITE_BCSR_1 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~);

MPC_WRITE_BCSR_3 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & A28 & A29 & !CntRegEn~);

"MPC_WRITE_BCSR_4 = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~);

BCSR_WRITE_ACTIVE = 0;

MPC_WRITE_BCSR_0 = (Bcsr0Write~.fb == BCSR_WRITE_ACTIVE);

MPC_WRITE_BCSR_1 = (Bcsr1Write~.fb == BCSR_WRITE_ACTIVE);

MPC_WRITE_BCSR_4 = (Bcsr4Write~.fb == BCSR_WRITE_ACTIVE);

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

MPC821 датащи(PDF) 107 Page - NXP Semiconductors