CS47L35 datasheet(196/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.16 Clocking and Sample Rates

The main loop takes a constant and stable clock reference as its input. For best performance, a high-frequency (e.g.,

12.288 MHz) reference is recommended. The main FLL loop is free running without any clock reference if the input signal

is removed; it can also be configured to initiate an output in the absence of any reference signal.

The synchronizer loop takes a separate clock reference as its input. The synchronizer input may be intermittent (e.g.,

during voice calls only). The FLL uses the synchronizer input, when available, as the frequency reference. To achieve the

designed performance advantage, the synchronizer input must be synchronous with the audio data.

Note that, if only a single clock input reference is used, this must be configured as the main FLL input reference. The

synchronizer should be disabled in this case.

The synchronizer loop should only be used when the main loop clock reference is present. If the input reference to the

main FLL is intermittent, or may be interrupted unexpectedly, the synchronizer should be disabled.

4.16.9.2 FLL Enable

The FLL is enabled by setting FLL1_ENA. The FLL synchronizer is enabled by setting FLL1_SYNC_ENA. The FLL should

be fully configured before setting the FLL1_ENA bit—this should be set as the final step of the FLL-enable sequence.

The FLL1_SYNC_ENA bit should not be changed if FLL1_ENA is set—the FLL1_ENA bit should be cleared before setting

or clearing FLL1_SYNC_ENA.

The FLL supports configurable free-running operation, using the FLL1_FREERUN bit described in Section 4.16.9.7. Note

that, once the FLL output has been established, the FLL is always free running if the input reference clock is stopped,

regardless of the FLL1_FREERUN bit.

To disable the FLL while the input reference clock has stopped, FLL1_FREERUN must be set before clearing the FLL1_

ENA bit.

When changing any of the FLL-configuration fields, it is recommended to disable the FLL by clearing the FLL1_ENA bit

before updating the other register fields; the FLL1_ENA bit should remain cleared until after the FLL has been

reconfigured. If the FLL configuration is changed while the FLL is enabled, the FLL1_FREERUN bit should be set before

updating any other FLL fields. A minimum delay of 32

s should be allowed between setting FLL1_FREERUN and writing

to the required FLL register fields. The FLL1_FREERUN bit should remain set until after the FLL has been reconfigured.

Note that, if the FLL1_N or FLL1_THETA fields are changed while the FLL is enabled, the FLL1_CTRL_UPD bit must also

be written, as described in Section 4.16.9.4. As a general rule, however, it is recommended to configure the FLL (and FLL

synchronizer, if applicable), before setting the FLL1_ENA bit.

The FLL configuration is shown in Fig. 4-65.

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