CS47L35 datasheet(183/300 Pages) CIRRUS

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DS1085F3

183

CS47L35

4.15 Interrupts

R6422 (0x1916)

IRQ2_Status_23

3 EVENT4_FULL_EINT2

Event Log 4 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

2 EVENT3_FULL_EINT2

Event Log 3 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 EVENT2_FULL_EINT2

Event Log 2 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 EVENT1_FULL_EINT2

Event Log 1 FIFO Full Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6423 (0x1917)

IRQ2_Status_24

3 EVENT4_WMARK_EINT2

Event Log 4 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

2 EVENT3_WMARK_EINT2

Event Log 3 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 EVENT2_WMARK_EINT2

Event Log 2 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 EVENT1_WMARK_EINT2

Event Log 1 FIFO Watermark Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6424 (0x1918)

IRQ2_Status_25

2 DSP3_DMA_EINT2

DSP3 DMA Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_DMA_EINT2

DSP2 DMA Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_DMA_EINT2

DSP1 DMA Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6426 (0x191A)

IRQ2_Status_27

2 DSP3_START1_EINT2

DSP3 Start 1 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_START1_EINT2

DSP2 Start 1 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_START1_EINT2

DSP1 Start 1 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6427 (0x191B)

IRQ2_Status_28

2 DSP3_START2_EINT2

DSP3 Start 2 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_START2_EINT2

DSP2 Start 2 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_START2_EINT2

DSP1 Start 2 Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6429 (0x191D)

IRQ2_Status_30

2 DSP3_BUSY_EINT2

DSP3 Busy Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

1 DSP2_BUSY_EINT2

DSP2 Busy Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

0 DSP1_BUSY_EINT2

DSP1 Busy Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6430 (0x191E)

IRQ2_Status_31

0 MIF1_DONE_EINT2

MIF1 Done Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6431 (0x191F)

IRQ2_Status_32

0 MIF1_BLOCK_EINT2

MIF1 Block Interrupt (Rising edge triggered)

Note: Cleared when a 1 is written.

R6464 (0x1940)

R6495 (0x195F)

IM_*

For each x_EINT2 interrupt bit in R6400 to R6431, a

corresponding mask bit (IM_*) is provided in R6464 to R6495.

The mask bits are coded as follows:

0 = Do not mask interrupt

1 = Mask interrupt

R6528 (0x1980)

IRQ2_Raw_

Status_1

12 CTRLIF_ERR_STS2

Control Interface Error Status

0 = Normal

1 = Control Interface Error

7 BOOT_DONE_STS2

Boot Status

0 = Busy (boot sequence in progress)

1 = Idle (boot sequence completed)

Control register writes should not be attempted until Boot

Sequence has completed.

Table 4-90. Interrupt 2 Control Registers (Cont.)

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