CS47L35 datasheet(169/300 Pages) CIRRUS

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DS1085F3

169

CS47L35

4.14 General-Purpose I/O

4.14.7 Interrupt (IRQ) Status Output—GPn_FN = 0x003, 0x004

The CS47L35 has an interrupt controller, which can be used to indicate when any selected interrupt events occur.

Individual interrupts may be masked in order to configure the interrupt as required. See Section 4.15 for full definition of

all supported interrupt events.

The interrupt controller supports two separate interrupt request (IRQ) outputs. The IRQ1 or IRQ2 status may be output

directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1.

Note that the IRQ1 status is output on the IRQ pin at all times.

4.14.8 Frequency-Locked Loop (FLL) Clock Output—GPn_FN = 0x010

A clock output derived from the FLL may be output on a GPIO pin. The GPIO output from the FLL is controlled by FLL1_

GPCLK_DIV and FLL1_GPCLK_ENA, as described in Table 4-86.

It is recommended to disable the clock output (FLL1_GPCLK_ENA = 0) before making any change to the FLL1_GPCLK_

DIV field.

Note that FLL1_GPCLK_DIV and FLL1_GPCLK_ENA affect the GPIO outputs only; they do not affect the FLL frequency.

The maximum output frequency supported for GPIO output is noted in Table 3-10.

The FLL clock output may be output directly on a GPIO pin by setting the respective GPIO fields as described in

Section 4.14.1.

See Section 4.16 for details of the CS47L35 system clocking and how to configure the FLL.

4.14.9 Frequency-Locked Loop (FLL) Status Output—GPn_FN = 0x018

The CS47L35 provides an FLL status flag, which may be used to control other events. The FLL lock signal indicates

whether FLL lock has been achieved. See Section 4.16.9 for details of the FLL.

The FLL lock signal may be output directly on a GPIO pin by setting the respective GPIO fields as described in

Section 4.14.1.

The FLL lock signal is an input to the interrupt controller circuit. An interrupt event is triggered on the rising and falling

edges of this signal. The associated interrupt bits are latched once set; they can be polled at any time or used to control

the IRQ signal. See Section 4.15 for details of the interrupt event handling.

4.14.10 OPCLK Clock Output—GPn_FN = 0x040

A clock output (OPCLK) derived from SYSCLK can be output on a GPIO pin. The OPCLK frequency is controlled by

OPCLK_DIV and OPCLK_SEL. The OPCLK output is enabled by setting OPCLK_ENA, as described in Table 4-87.

It is recommended to disable the clock output (OPCLK_ENA = 0) before making any change to OPCLK_DIV or OPCLK_

SEL.

Table 4-86. FLL Clock Output Control

Bit

Label

Default

Description

R392 (0x0188)

FLL1_GPIO_Clock

7:1 FLL1_GPCLK_

DIV[6:0]

0x06

FLL1 GPIO Clock Divider

0x00 to 0x05 = Reserved

0x06 = Divide by 6

0x07 = Divide by 7

0x08 = Divide by 8

0x09 = Divide by 9

…

0x7F = Divide by 127

(FGPIO = FVCO/FLL1_GPCLK_DIV)

FLL1_GPCLK_

ENA

FLL1 GPIO Clock Enable

0 = Disabled

1 = Enabled

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