CS47L35 datasheet(165/300 Pages) CIRRUS

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CS47L35

4.14 General-Purpose I/O

Logic input and output (GPIO) can be supported in two different ways on the CS47L35. The standard mechanism

described in this section provides a comprehensive suite of options including input debounce, and selectable output drive

configuration. The DSP GPIO circuit is tailored towards more advanced requirements typically demanded by DSP software

features. The DSP GPIO functions are described in Section 4.5.4.

The CS47L35 also incorporates a general-purpose switch feature, which can be used as a controllable analog switch, as

described in Section 4.14.16.

4.14.1 GPIO Control

For each GPIO, the selected function is determined by the GPn_FN field, where n identifies the GPIO pin (1–16). The pin

direction, set by GPn_DIR, must be set according to function selected by GPn_FN.

If a pin is configured as a GPIO input (GPn_DIR = 1, GPn_FN = 0x001), the logic level at the pin can be read from the

respective GPn_LVL bit. Note that GPn_LVL is not affected by the GPn_POL bit.

A debounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin by setting

the respective GPn_DB bit. The debounce circuit uses the 32-kHz clock, which must be enabled whenever input debounce

functions are required. The debounce time is configurable using the GP_DBTIME field. See Section 4.16 for further details

of the CS47L35 clocking configuration.

Each of the GPIO pins is an input to the interrupt control circuit and can be used to trigger an interrupt event. An interrupt

event is triggered on the rising and falling edges of the GPIO input. The associated interrupt bit is latched once set; it can

be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling.

Integrated pull-up and pull-down resistors are provided on each of the GPIO pins; these can be configured independently

using the GPn_PU and GPn_PD fields. When the pull-up and pull-down control bits are both enabled, the CS47L35

provides a bus keeper function on the respective pin. The bus keeper function holds the logic level unchanged whenever

the pin is undriven (e.g., if the signal is tristated).

Note: The bus keeper is enabled by default on all GPIO pins and, if not actively driven, may result in either a Logic 0 or

Logic 1 at the respective input on start-up. If an external pull resistor is connected (e.g., to control the logic level

in Sleep Mode), the chosen resistance should take account of the bus keeper resistance (see Table 3-10). A

strong pull resistor (e.g., 10 k

) is required, if a specific start-up condition is to be forced by the external pull

component.

If a pin is configured as a GPIO output (GPn_DIR = 0, GPn_FN = 0x001), its level can be set to Logic 0 or Logic 1 using

the GPn_LVL field. Note that the GPn_LVL bits are write-only when the respective GPIO pin is configured as an output.

If a pin is configured as an output (GPn_DIR = 0), the polarity can be inverted using the GPn_POL bit. When GPn_

POL = 1, the selected output function is inverted. In the case of logic level output (GPn_FN = 0x001), the external output

is the opposite logic level to GPn_LVL when GPn_POL = 1. Note that, if GPn_FN = 0x000 or 0x002, the GPn_POL bit has

no effect on the respective GPIO pin.

A GPIO output can be either CMOS driven or open drain. This is selected on each pin using the respective GPn_OP_CFG

bit. Note that if GPn_FN = 0x000 the GPn_OP_CFG bit has no effect on the respective GPIO pin—see Table 4-83 for

further details. If GPn_FN = 0x002, the respective pin output is CMOS.

The register fields that control the GPIO pins are described in Table 4-83.

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