CS47L35 datasheet(168/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.14 General-Purpose I/O

4.14.4 Button Detect (GPIO Input)—GPn_FN = 0x001

Button-detect functionality can be selected on a GPIO pin by setting the respective GPIO fields as described in

Section 4.14.1. The same functionality can be used to support a jack-detect input function.

It is recommended to enable the GPIO input debounce feature when using GPIOs as button input or jack-detect input.

The GPn_LVL fields may be read to determine the logic levels on a GPIO input, after the selectable debounce controls.

Note that GPn_LVL is not affected by the GPn_POL bit.

The debounced GPIO signals are also inputs to the interrupt-control circuit. An interrupt event is triggered on the rising

and falling edges of the GPIO input. The associated interrupt bits are latched once set; they can be polled at any time or

used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling.

4.14.5 Logic 1 and Logic 0 Output (GPIO Output)—GPn_FN = 0x001

The CS47L35 can be programmed to drive a logic high or logic low level on a GPIO pin by selecting the GPIO Output

function as described in Section 4.14.1.

The output logic level is selected using the respective GPn_LVL bit. Note that, if a GPIO pin is configured as an output,

the respective GPn_LVL bits are write-only.

The polarity of the GPIO output can be inverted using the GPn_POL bits. If GPn_POL = 1, the external output is the

opposite logic level to GPn_LVL.

4.14.6 DSP GPIO (Low-Latency DSP Input/Output)—GPn_FN = 0x002

The DSP GPIO function provides an advanced I/O capability, supporting the requirements of the CS47L35 as a

multipurpose sensor hub. The DSP GPIO pins are accessed using maskable sets of I/O control registers; this allows the

selected combinations of GPIOs to be controlled with ease, regardless of how the allocation of GPIO pins has been

implemented in hardware.

The DSP GPIO function is selected by setting the respective GPIO fields as described in Section 4.14.1.

A full description of the DSP GPIO function is provided in Section 4.5.4.

Note that, if GPn_FN is set to 0x002, the respective pin direction (input or output) is set according to the DSP GPIO

configuration for that pin—the GPn_DIR control bit has no effect in this case.

Table 4-85. GPIO Alternate Functions

Name

Condition

Description

Direction

Output Driver

Configuration

AIF1BCLK/GPIO9

GP9_FN = 0x000

Audio Interface 1 bit clock

Digital I/OCMOS

AIF1LRCLK/GPIO11

GP11_FN = 0x000

Audio Interface 1 left/right clock

Digital I/O

CMOS

AIF1RXDAT/GPIO8

GP8_FN = 0x000

Audio Interface 1 RX digital audio data Digital input

CMOS

AIF1TXDAT/GPIO10

GP10_FN = 0x000

Audio Interface 1 TX digital audio data Digital output

CMOS

AIF2BCLK/GPIO13

GP13_FN = 0x000

Audio Interface 2 bit clock

Digital I/O

CMOS

AIF2LRCLK/GPIO15

GP15_FN = 0x000

Audio Interface 2 left/right clock

Digital I/O

CMOS

AIF2RXDAT/GPIO14

GP14_FN = 0x000

Audio Interface 2 RX digital audio data Digital input

CMOS

AIF2TXDAT/GPIO12

GP12_FN = 0x000

Audio Interface 2 TX digital audio data Digital output

CMOS

AIF3BCLK/GPIO2

GP2_FN = 0x000

Audio Interface 3 bit clock

Digital I/OCMOS

AIF3LRCLK/GPIO4

GP4_FN = 0x000

Audio Interface 3 left/right clock

Digital I/O

CMOS

AIF3RXDAT/GPIO3

GP3_FN = 0x000

Audio Interface 3 RX digital audio data Digital input

CMOS

AIF3TXDAT/GPIO1

GP1_FN = 0x000

Audio Interface 3 TX digital audio data Digital output

CMOS

MIF1SCLK/GPIO16

GP16_FN = 0x000

Master (I2C) Interface 1 clock

Digital output

Open drain

MIF1SDA/GPIO7

GP7_FN = 0x000

Master (I2C) Interface 1 data

Digital I/O

Open drain

SPKCLK/GPIO6

GP6_FN = 0x000

Digital speaker (PDM) clock

Digital output

CMOS

SPKDAT/GPIO5

GP5_FN = 0x000

Digital speaker (PDM) data

Digital outputCMOS

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