CS47L35 datasheet(172/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.15 Interrupts

The switch is a bidirectional analog switch, offering flexibility in the potential circuit applications. Refer to Table 3-2 and

Table 3-10 for further details.

The switch can be used in conjunction with the MICDET clamp function to suppress pops and clicks associated with jack

insertion and removal. An example circuit is shown in Fig. 4-58 within the External Accessory Detection section. Note that

the MICDET clamp function must also be configured appropriately when using this method of pop suppression.

4.15 Interrupts

The interrupt controller has multiple inputs. These include the jack detect and GPIO input pins, DSP_IRQn flags,

headphone/accessory detection, FLL lock detection, and status flags from DSP peripheral functions. See Table 4-89 and

Table 4-90 for a full definition of the interrupt controller inputs. Any combination of these inputs can be used to trigger an

interrupt request event.

The interrupt controller supports two sets of interrupt registers. This allows two separate interrupt request (IRQ) outputs

to be generated, and for each IRQ to report a different set of input or status conditions.

For each interrupt request (IRQ1 and IRQ2) output, there is an interrupt register field associated with each of the interrupt

inputs. These fields are asserted whenever a logic edge is detected on the respective input. Some inputs are triggered on

rising edges only; some are triggered on both edges. Separate rising and falling interrupt bits are provided for the JD1 and

JD2 signals. The interrupt register fields for IRQ1 are described in Table 4-89. The interrupt register fields for IRQ2 are

described in Table 4-90. The interrupt flags can be polled at any time or in response to the interrupt request output being

signaled via the IRQ pin or a GPIO pin.

All interrupts are edge triggered, as noted above. Many are triggered on both the rising and falling edges and, therefore,

the interrupt bits cannot indicate which edge has been detected. The raw status fields described in Table 4-89 and

Table 4-90 indicate the current value of the corresponding inputs to the interrupt controller. Note that the raw status bits

associated with IRQ1 and IRQ2 provide the same information. The status of any GPIO (or DSP GPIO) inputs can also be

read using the GPIO (or DSP GPIO) control fields, as described in Table 4-83 and Table 4-34.

Individual mask bits can enable or disable different functions from the interrupt controller. The mask bits are described in

Table 4-89 (for IRQ1) and Table 4-90 (for IRQ2). Note that a masked interrupt input does not assert the corresponding

interrupt register field and does not cause the associated interrupt request output to be asserted.

The interrupt request outputs represent the logical OR of the associated interrupt registers. IRQ1 is derived from the x_

EINT1 registers; IRQ2 is derived from the x_EINT2 registers. The interrupt register fields are latching fields and, once they

are set, they are not reset until a 1 is written to the respective bits. The interrupt request outputs are not reset until each

of the associated interrupts has been reset.

A debounce circuit can be enabled on any GPIO input, to avoid false event triggers. This is enabled on each pin using the

fields described in Table 4-83. The GPIO debounce circuit uses the 32-kHz clock, which must be enabled whenever the

GPIO debounce function is required.

A debounce circuit is always enabled on the FLL status inputs; to trigger an interrupt from the FLL status inputs, the 32-kHz

clock or the SYSCLK signal must be enabled. Note that the raw status fields (described in Table 4-89 and Table 4-90) are

valid without clocking, and can be used to provide FLL status indication when system clocks are not available.

The IRQ outputs can be globally masked using the IM_IRQ1 and IM_IRQ2 bits. When not masked, the IRQ status can be

read from IRQ1_STS and IRQ2_STS for the respective IRQ outputs.

Table 4-88. General-Purpose Switch Control

Bit

Label

Default

Description

R712 (0x02C8)

GP_Switch_1

1:0

SW1_MODE[1:0]

General-purpose Switch control

00 = Disabled (open)

01 = Enabled (closed)

10 = Enabled when MICDET clamp is active

11 = Enabled when MICDET clamp is not active

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