CS47L35 datasheet(173/300 Pages) CIRRUS

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DS1085F3

173

CS47L35

4.15 Interrupts

The IRQ1 output is provided externally on the IRQ pin. Under default conditions, this output is active low. The polarity can

be inverted using IRQ_POL. The IRQ output can be either CMOS driven or open drain; this is selected using the IRQ_

OP_CFG bit. The IRQ output is referenced to the DBVDD1 power domain.

The IRQ2 status can be used to trigger DSP firmware execution; see Section 4.4. This allows the DSP firmware execution

to be linked to external events (e.g., jack detection, or GPIO input), or to any of the status conditions flagged by the

interrupt registers.

The IRQ1 and IRQ2 signals may be output on a GPIO pin; see Section 4.14.

The CS47L35 interrupt controller circuit is shown in Fig. 4-62. (Note that not all interrupt inputs are shown.) The control

fields associated with IRQ1 and IRQ2 are described in Table 4-89 and Table 4-90 respectively. The global interrupt mask

bits, status bits, and output configuration fields are described Table 4-91.

Note that, under default register conditions, the boot done status is the only unmasked interrupt source; a falling edge on

the IRQ pin indicates completion of the boot sequence.

Figure 4-62. Interrupt Controller

IM_xxx_EINT1

IM_GP1_EINT1

IM_FLL1_LOCK_EINT1

IM_DRC1_SIG_DET_EINT1

IM_DSP_IRQ1_EINT1

xxx_EINT1

GP1_EINT1

FLL1_LOCK_EINT1

DRC1_SIG_DET_EINT1

DSP_IRQ1_EINT1

IM_IRQ1

IRQ1_STS

xxx_STSn

GP1_LVLn

FLL1_LOCK_STSn

DRC1_SIG_DET_STSn

DSP_IRQ1_STSn

IM_xxx_EINT2

IM_GP1_EINT2

IM_FLL1_LOCK_EINT2

IM_DRC1_SIG_DET_EINT2

IM_DSP_IRQ1_EINT2

xxx_EINT2

GP1_EINT2

FLL1_LOCK_EINT2

DRC1_SIG_DET_EINT2

DSP_IRQ1_EINT2

IM_IRQ2

IRQ2_STS

Note: not all available interrupt sources are shown

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