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CS47L35 датащи(PDF) 171 Page - Cirrus Logic |
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CS47L35 датащи(HTML) 171 Page - Cirrus Logic |
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171 / 300 page ![]() DS1085F3 171 CS47L35 4.14 General-Purpose I/O 4.14.13 Overtemperature, Short-Circuit Protection, and Speaker Shutdown Status Output— GPn_FN = 0x0B6, 0x0E0, 0x0E1, 0x0E2. The CS47L35 incorporates a temperature sensor, which detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The temperature status may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. A GPIO pin can be used to indicate either an Overheat Warning Temperature event or an Overheat Shutdown Temperature event. The CS47L35 provides short-circuit protection on the Class D speaker outputs, and on each of the headphone output paths. The status of the Class D speaker short-circuit detection circuits may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. If the Overheat Shutdown Temperature is exceeded, or if a short circuit is detected on the Class D speaker outputs, the Class D speaker outputs are automatically disabled in order to protect the device. The general-purpose timers can be used as a watchdog function to trigger a shutdown of the Class D speaker drivers. Further details of the Speaker Shutdown functions are described in Section 4.21. When the speaker driver shutdown is complete, the Speaker Shutdown signal is asserted. The speaker driver shutdown status can also be output directly on a GPIO pin. The Overtemperature, short-circuit protection, and Speaker Shutdown status flags are inputs to the interrupt control circuit. An interrupt event may be triggered on the applicable edges of these signals. The associated interrupt bit is latched once set; it can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.14 General-Purpose Timer Status Output—GPn_FN = 0x140–0x143 The general-purpose timers can count up or down, and support continuous or single count modes. Status outputs indicating the progress of these timers are provided. See Section 4.5.3 for details of the general-purpose timers. A logic signal from the general-purpose timers may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1 . This logic signal is pulsed high whenever the respective timer reaches its final count value. The general-purpose timers also provide inputs to the interrupt control circuit. An interrupt event is triggered whenever the respective timer reaches its final count value. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.15 Event Logger FIFO Buffer Status Output—GPn_FN = 0x150–0x153 The event loggers are each provided with a 16-stage FIFO buffer, in which any detected events (signal transitions) are recorded. Status outputs for each FIFO buffer are provided. See Section 4.5.2 for details of the event loggers. A logic signal from the event loggers may be output directly on a GPIO pin by setting the respective GPIO fields as described in Section 4.14.1. This logic signal is set high whenever the FIFO not-empty condition is true. The event loggers also provide inputs to the interrupt control circuit. An interrupt event is triggered whenever the respective FIFO condition occurs. The associated interrupt bits are latched once set; they can be polled at any time or used to control the IRQ signal. See Section 4.15 for details of the interrupt event handling. 4.14.16 General-Purpose Switch The CS47L35 provides a general-purpose switch, which can be used as a controllable analog switch for external functions. The switch is implemented between the GPSWP and GPSWN pins. Note that this feature is entirely independent of the GPIOn pins. The general-purpose switch is configured using SW1_MODE. This field allows the switch to be disabled, enabled, or synchronized to the MICDET clamp status, as described in Table 4-88. |
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