CS47L35 datasheet(170/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.14 General-Purpose I/O

The OPCLK output should be kept disabled (OPCLK_ENA = 0) if SYSCLK is not enabled. SYSCLK must be present and

enabled before setting the OPCLK_ENA bit. See Section 4.16.4 for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

The OPCLK clock can be output directly on a GPIO pin by setting the respective GPIO fields as described in

Section 4.14.1.

Note that the OPCLK source frequency cannot be higher than the SYSCLK frequency. The maximum output frequency

supported for GPIO output is noted in Table 3-10.

See Section 4.16 for details of the SYSCLK system clock.

4.14.11 Pulse-Width Modulation (PWM) Signal Output—GPn_FN = 0x048, 0x049

The CS47L35 incorporates two PWM signal generators, which can be enabled as GPIO outputs. The duty cycle of each

PWM signal can be modulated by an audio source, or can be set to a fixed value using a control register setting.

The PWM outputs may be output directly on a GPIO pin by setting the respective GPIO fields as described in

Section 4.14.1.

See Section 4.3.12 for details of how to configure the PWM signal generators.

4.14.12 S/PDIF Audio Output—GPn_FN = 0x04C

The CS47L35 incorporates an IEC-60958-3–compatible S/PDIF transmitter, which can be selected as a GPIO output. The

S/PDIF transmitter supports stereo audio channels and allows full control over the S/PDIF validity bits and channel status

information.

The S/PDIF signal may be output directly on a GPIO pin by setting the respective GPIO fields as described in

Section 4.14.1.

See Section 4.3.8 for details of how to configure the S/PDIF output generator.

Table 4-87. OPCLK Control

Bit

Label

Default

Description

R329 (0x0149)

Output_system_

clock

OPCLK_ENA

OPCLK Enable

0 = Disabled

1 = Enabled

7:3

OPCLK_DIV[4:0]

0x00 OPCLK Divider

0x02 = Divide by 2

0x04 = Divide by 4

0x06 = Divide by 6

… (even numbers only)

0x1E = Divide by 30

Note that only even numbered divisions (2, 4, 6, etc.) are valid selections.

All other codes are reserved when the OPCLK signal is enabled.

2:0

OPCLK_SEL[2:0]

000

OPCLK Source Frequency

000 = 6.144 MHz (5.6448 MHz)

001 = 12.288 MHz (11.2896 MHz)

010 = 24.576 MHz (22.5792 MHz)

011 = 49.152 MHz (45.1584 MHz)

All other codes are reserved

The frequencies in brackets apply for 44.1 kHz–related SYSCLK rates only (i.e.,

SAMPLE_RATE_n =01XXX).

The OPCLK Source Frequency must be less than or equal to the SYSCLK

frequency.

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