CS47L35 datasheet(164/300 Pages) CIRRUS

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DS1085F3

CS47L35

4.14 General-Purpose I/O

The always-on functionality includes the JD1 and JD2 control signals, which provide support for the low-power Sleep

Mode. The MICDET clamp status signal is also supported; this is controlled by a selectable logic function, derived from

JD1 and/or JD2.

The JD1, JD2 and MICDET clamp status signals are derived from the JACKDET1 and JACKDET2 inputs, and can be used

to trigger the interrupt controller.

• The JD1 and JD2 signals are derived from the jack detect function (see Section 4.12). These inputs can be used to

trigger a response to a jack insertion or jack removal detection.

When these signals are enabled, the JD1 and JD2 signals indicate the status of the JACKDET1 and JACKDET2

input pins respectively. See Table 4-74 for details of the associated control fields.

• The MICDET clamp status is controlled by the JD1 and/or JD2 signals (see Section 4.12). The configurable logic

provides flexibility in selecting the appropriate conditions for activating the MICDET clamp. The clamp status can

be used to trigger a response to a jack insertion or jack removal detection.

The MICDET clamp function is configured using MICD_CLAMP_MODE, as described in Table 4-75.

The interrupt functionality associated with these signals is part of the always-on functionality, enabling the CS47L35 to

provide indication of jack insertion or jack removal to the host processor in Sleep Mode; see Section 4.15.

Note that the JACKDET1 and JACKDET2 inputs do not result in a wake-up transition directly; a wake-up transition only

occurs by reapplication of DCVDD. In a typical application, the JACKDETn inputs provide a signal to the applications

processor, via the IRQ output; if a wake-up transition is required, this is triggered by the applications processor enabling

the DCVDD supply.

4.14 General-Purpose I/O

The CS47L35 provides a number of GPIO functions to enable interfacing and detection of external hardware and to

provide logic outputs to other devices. The GPIO input functions can be used to generate an interrupt (IRQ) event. The

GPIO and interrupt circuits support the following functions:

• Pin-specific alternative functions for external interfaces (AIF, DMIC, PDM, MIF)

• Logic input/button detect (GPIO input)

• Logic 1 and Logic 0 output (GPIO output)

• Interrupt (IRQ) status output

• Clock output

• Frequency-locked loop (FLL) status output

• FLL clock output

• IEC-60958-3–compatible S/PDIF output

• Pulse-width modulation (PWM) signal output

• Overtemperature, speaker short-circuit protection, and speaker shutdown status output

• General-purpose timer status output

• Event logger FIFO buffer status output

Note that the GPIO pins are referenced to different power domains (DBVDD1 or DBVDD2), as indicated in Table 1-1.

Table 4-82. Sleep Mode Always-On Digital Input/Output Pins

Pin Name

Description

Reference

IRQ

Interrupt Request output

See Section 4.15

JACKDET1

Jack Detect input 1

See Section 4.12

JACKDET2

Jack Detect input 2

See Section 4.12

RESET

Digital Reset input (active low)

See Section 4.23

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