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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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K32L2AX датащи(PDF) 13 Page - NXP Semiconductors |
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K32L2AX датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 96 page  Table 4. Peripheral Clocks (continued) Source Module Module Reset Bus Interface Clock Bus Interface Clock Gating Control Peripheral Functional Clock PCCn Functional Clock Divider SRAM Chip Reset DIVCORE_CLK System Register File POR DIVSLOW_CLK Analog TSI Chip Reset not VLLS DIVSLOW_CLK Yes ADC Chip Reset DIVSLOW_CLK Yes SCG DIV3 VREF Chip Reset DIVSLOW_CLK Yes DAC Chip Reset DIVSLOW_CLK Yes CMP Chip Reset DIVSLOW_CLK Yes Timers TPM Chip Reset DIVSLOW_CLK Yes SCG DIV3 LPIT Chip Reset DIVSLOW_CLK Yes SCG DIV3 Low-Power Timer (LPTMR)3 POR/LVD DIVSLOW_CLK Yes LPO, ERCLK2, SIRC, OSC32KCLK Real-time Clock (RTC)4 POR DIVSLOW_CLK Yes OSC32KCLK, LPO TSTMR Chip Reset DIVSLOW_CLK SIRCLK @ 1 MHz Communications USB Chip Reset DIVCORE_CLK5 Yes SCG DIV1, USB_CLKIN 6 3-bit Divide, 1-bit Fraction 7 LPSPI Chip Reset DIVSLOW_CLK Yes SCG DIV3 LPI2C Chip Reset DIVSLOW_CLK Yes SCG DIV3 LPUART Chip Reset DIVSLOW_CLK Yes SCG DIV3 EMVSIM Chip Reset DIVSLOW_CLK Yes SCG DIV3 FlexIO Chip Reset DIVSLOW_CLK Yes SCG DIV3 GPIO controller Chip Reset DIVCORE_CLK 1. Watchdog clock sources are selected by WDOGx_CS[CLK] 2. ERCLK is either from an external pin or from the SCG Internal OSC (SOSC) and configured with the SCG_SOSCCFG[EREFS] bit. 3. LPTMR clock sources are selected by LPTMR_PSR[PCS] 4. RTC clock sources are selected by RTC_CR[LPOS] 5. For the USB FS OTG controller to operate, the minimum required DIVCORE_CLK is 24 MHz (half of USB functional clock) 6. An additional external clock USB_CLKIN, can also selected via PCCUSB0FS, and device's PORTx MUX field 7. Additional 3bit Divide field and 1-bit Fractional field reside in PCCUSB0FS register Overview K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021 13 NXP Semiconductors |
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