K32L2AX datasheet(70/96 Pages) NXP

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8.6.4.2 12-bit DAC operating behaviors

Table 42. 12-bit DAC operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

IDDA_DACL

Supply current — low-power mode

—

250

μA

IDDA_DACH

Supply current — high-speed mode

—

900

μA

tDACLP

Full-scale settling time (0x080 to 0xF7F) —

low-power mode

—

100

200

μs

tDACHP Full-scale settling time (0x080 to 0xF7F) —

high-power mode

—

μs

tCCDACLP Code-to-code settling time (0xBF8 to

0xC08) — low-power mode and high-speed

mode

—

0.7

μs

Vdacoutl DAC output voltage range low — high-

speed mode, no load, DAC set to 0x000

—

100

Vdacouth DAC output voltage range high — high-

speed mode, no load, DAC set to 0xFFF

VDACR

−100

—

VDACR

INL

Integral non-linearity error — high speed

mode

—

±8

LSB

DNL

Differential non-linearity error — VDACR > 2

—

±1

LSB

DNL

Differential non-linearity error — VDACR =

VREF_OUT

—

±1

LSB

VOFFSET Offset error

—

±0.4

±0.8

%FSR

Gain error

—

±0.1

±0.6

%FSR

PSRR

Power supply rejection ratio, VDDA ≥ 2.4 V

—

TCO

Temperature coefficient offset voltage

—

3.7

—

μV/C

TGE

Temperature coefficient gain error

—

0.000421

—

%FSR/C

Rop

Output resistance (load = 3 kΩ)

—

250

Slew rate -80h→ F7Fh→ 80h

• High power (SPHP)

• Low power (SPLP)

1.2

0.05

1.7

0.12

—

V/μs

3dB bandwidth

• High power (SPHP)

• Low power (SPLP)

550

—

kHz

1. Settling within ±1 LSB

2. The INL is measured for 0 + 100 mV to VDACR −100 mV

3. The DNL is measured for 0 + 100 mV to VDACR −100 mV

4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V

5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV

6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set

to 0x800, temperature range is across the full range of the device

Peripheral operating requirements and behaviors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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