K32L2AX datasheet(51/96 Pages) NXP

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Table 21. General switching specifications

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter disabled)

— Synchronous path

1.5

—

Bus clock

cycles

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter enabled) — Asynchronous path

100

—

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter disabled) — Asynchronous path

—

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100

—

GPIO pin interrupt pulse width — Asynchronous path

—

Port rise/fall time

Normal drive pins

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

• Slow slew rate

—

10.5

High drive pins

Normal/low drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

• Slow slew rate

High drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

• Slow slew rate

—

2.5

10.5

2.5

Normal drive fast pins

• 2.7 ≤ VDD ≤ 3.6 V

• Fast slew rate

• Slow slew rate

• 1.71 ≤ VDD ≤ 2.7 V

• Fast slew rate

• Slow slew rate

—

0.5

0.75

High drive fast pins

Normal/low drive enabled

• 2.7 ≤ VDD ≤ 3.6 V

—

0.5

General

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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