K32L2AX datasheet(7/96 Pages) NXP

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2.1.1 Arm Cortex-M0+ core

The enhanced Arm Cortex M0+ is the member of the Cortex-M series of processors

targeting microcontroller cores focused on very cost sensitive, low power

applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC

component. It also has hardware debug functionality including support for simple

program trace capability. The processor supports the Armv6-M instruction set

(Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus

seven 32-bit instructions. It is upward compatible with other Cortex-M profile

processors.

2.1.2 NVIC

The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority

levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It

also differs in number of interrupt sources and supports 32 interrupt vectors.

The Cortex-M family uses a number of methods to improve interrupt latency to up to

15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait

and VLPW modes.

2.1.3 AWIC

The asynchronous wake-up interrupt controller (AWIC) is used to detect

asynchronous wake-up events in Stop mode and signal to clock control logic to

resume system clocking. After clock restarts, the NVIC observes the pending interrupt

and performs the normal interrupt or event processing. The AWIC can be used to

wake MCU core from Stop and VLPS modes.

Wake-up sources are listed as below:

Table 2. AWIC stop wake-up sources

Wake-up source

Description

Available system resets

RESET pin when LPO is its clock source

Low-voltage detect

Power management controller—functional in Stop mode

Low-voltage warning

Power management controller—functional in Stop mode

Pin interrupts

Port control module—any enabled pin interrupt is capable of waking the system

ADC

The ADC is functional when using internal clock source

CMP

Interrupt in normal or trigger mode

Table continues on the next page...

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

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