K32L2AX datasheet(44/96 Pages) NXP

44 / 96 page

4. 72 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_RCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks disabled by clearing all xxDIV3, xxDIV2, and xxDIV1 in SCG_SOSCDIV and

SCG_SPLLDIV registers. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].

5. 48 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as FIRC 48 MHz mode (SCG_RCCR[SCS]=0011). All peripheral functional clocks disabled by clearing

all xxDIV3, xxDIV2, and xxDIV1 in SCG_FIRCDIV register. PLL, SOSC, and SIRC disabled by clearing

SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_SIRCCSR[SIRCEN].

6. 72 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as System PLL mode (SCG_RCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz

crystal. All peripheral functional clocks except USB = 24 MHz from SPLLDIV3_CLK. USB functional clock = 48 MHz

from SPLLDIV1_CLK. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].

7. 48 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.

SCG configured as FIRC 48 MHz mode (SCG_RCCR[SCS]=0011). All peripheral functional clocks except USB = 24

MHz from FIRCDIV3_CLK. USB functional clock = 48 MHz from FIRCDIV1_CLK. PLL, SOSC, and SIRC disabled by

clearing SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_SIRCCSR[SIRCEN].

8. 4 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks except USB = 1M Hz from

SIRCDIV3_CLK. USB clock disabled. PLL, SOSC, and FIRC disabled by clearing SCG_SPLLCSR[SPLLEN],

SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

9. 8 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks except USB = 1M Hz from

SIRCDIV3_CLK. USB clock disabled. PLL, SOSC, and FIRC disabled by clearing SCG_SPLLCSR[SPLLEN],

SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

10. 4 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks disabled by clearing all

xxDIV3, xxDIV2, and xxDIV1 in SCG_SIRCDIV register. PLL, SOSC, and FIRC disabled by clearing

SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

11. 8 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG

configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks disabled by clearing all

xxDIV3, xxDIV2, and xxDIV1 in SCG_SIRCDIV register. PLL, SOSC, and FIRC disabled by clearing

SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].

12. No brownout

Table 17. Low power mode peripheral adders — typical value

Symbol

Description

Temperature (°C)

Unit

-40

105

IEREFSTEN8MHz

External 8 MHz crystal clock adder with

System OSC. Measured by entering

VLPS mode with the crystal enabled

(SCG_SOSCCFG[RANGE] = 10,

SCG_SOSCCFG[HGO] = 0,

SCG_SOSCCFG[EREFS] = 1, and

SC2P/SC4P/SC8P = 0).

402.9

462.1

477.5

492

506.2

530.4

IEREFSTEN32KHz

External 32 kHz crystal clock adder with

System OSC by means of

SCG_SOSCCFG[RANGE] = 01,

SCG_SOSCCFG[HGO] = 0,

SCG_SOSCCFG[EREFS] = 1, and

SC2P/SC4P/SC8P = 0. Measured by

entering all the following modes with the

crystal enabled:

• VLLS1

• VLLS3

373.9

568.4

582.8

539.2

552.6

565.0

612.3

650.8

615.5

644.9

757.9

797.1

523.7

995.6

968.5

1000

1400

1700

Table continues on the next page...

General

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

K32L2AX датащи(PDF) 44 Page - NXP Semiconductors

K32L2AX датащи(HTML) 44 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

датащи скачать

ссылки URL