K32L2AX datasheet(81/96 Pages) NXP

81 / 96 page

<<CLASSIFICATION>>

<<NDA MESSAGE>>

MSB IN2

BIT 6 . . . 1

MASTER MSB OUT2

MASTER LSB OUT

PORT DATA

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

(OUTPUT)

(CPOL=0)

SPSCK

(CPOL=1)

SS1

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

LSB IN

BIT 6 . . . 1

Figure 23. LPSPI master mode timing (CPHA = 1)

Table 50. LPSPI slave mode timing on slew rate disabled pads

Num.

Symbol

Description

Min.

Max.

Unit

Note

fop

Frequency of operation

fperiph/4

tSPSCK

SPSCK period

4 x tperiph

—

tLead

Enable lead time

—

tperiph

—

tLag

Enable lag time

—

tperiph

—

tWSPSCK Clock (SPSCK) high or low time

tperiph - 30

—

tSU

Data setup time (inputs)

2.5

—

tHI

Data hold time (inputs)

3.5

—

Slave access time

—

tperiph

tdis

Slave MISO disable time

—

tperiph

Data valid (after SPSCK edge)

—

tHO

Data hold time (outputs)

—

tRI

Rise time input

—

tperiph - 25

—

tFI

Fall time input

tRO

Rise time output

—

tFO

Fall time output

1. fperiph is the LPSPI peripheral functional clock

2. tperiph = 1/fperiph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

Peripheral operating requirements and behaviors

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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