K32L2AX datasheet(27/96 Pages) NXP

27 / 96 page

Pinouts and Packaging

4.1 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is

responsible for selecting which ALT function is available on each pin.

NOTE

• A pull-up resistor (typically 4.7 KΩ) must be connected

to the EMVSIM0_IO pin if this pin is configured as

EMV SIM function.

• PTB0/1, PTC3/4, PTD4/5/6/7 have both high drive and

normal/low drive capability. PTD4, PTD5, PTD6,

PTD7, PTE20, PTE21, PTE22, PTE23 are also fast pins.

When a high bit rate is required on the communication

interface pins, it is recommended to use fast pins. In

case of high bus loading, the high drive strength of high

drive pins must be enabled by setting the corresponding

PORTx_PCRn[DSE] bit.

• RESET_b pin is open drain with internal pullup device

and passive analog filter when configured as RESET pin

(default state after POR). When this pin is configured to

other shared functions, the passive analog filter is

disabled.

• NMI0_b pin has pullup device enabled and passive

analog filter disabled after POR.

• SWD_DIO pin has pullup device enabled after POR.

SWD_CLK has pulldown device enabled after POR.

100

LQFP

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

PTE0

ADC0_SE16

PTE0/

RTC_CLKOUT

LPSPI1_SIN

LPUART1_TX

CMP0_OUT

LPI2C1_SDA

PTE1/

LLWU_P0

ADC0_SE17

PTE1/

LLWU_P0

LPSPI1_

SOUT

LPUART1_RX

LPI2C1_SCL

—

PTE2/

LLWU_P1

ADC0_SE18

PTE2/

LLWU_P1

LPSPI1_SCK

LPUART1_

CTS_b

LPI2C1_SDAS

—

PTE3

ADC0_SE19

PTE3

LPSPI1_SIN

LPUART1_

RTS_b

LPI2C1_SCLS

Pinouts and Packaging

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

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