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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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K32L2AX датащи(PDF) 62 Page - NXP Semiconductors |
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K32L2AX датащи(HTML) 62 Page - NXP Semiconductors |
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62 / 96 page  Table 34. 16-bit ADC operating conditions (continued) Symbol Description Conditions Min. Typ.1 Max. Unit Notes • fADCK > 8 MHz • fADCK = 4–8 MHz • fADCK < 4 MHz 13-bit / 12-bit modes • fADCK > 16 MHz • fADCK > 8 MHz • fADCK = 4–8 MHz • fADCK < 4 MHz 11-bit / 10-bit modes • fADCK > 8 MHz • fADCK = 4–8 MHz • fADCK < 4MHz 9-bit / 8-bit modes • fADCK > 8 MHz • fADCK < 8 MHz — — — — — — — — — — — — — — — — — — — — — — 1 2 0.5 1 2 5 2 5 10 5 10 kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ fADCK ADC conversion clock frequency ≤ 13-bit mode 1.0 — 24.0 MHz 5 16-bit mode 2.0 — 12.0 MHz Crate ADC conversion rate ≤ 13-bit modes No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 20.000 — 1200 ksps 6 Crate ADC conversion rate 16-bit mode No ADC hardware averaging Continuous conversions enabled, subsequent conversion time 37.037 — 461.467 ksps 6 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. DC potential difference. 3. Assumes ADLSMP=0 4. This resistance is external to the MCU. To achieve the best results, the analog source resistance must be kept as low as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS * CAS time constant should be kept to < 1 ns. 5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. 6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool. Peripheral operating requirements and behaviors 62 K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021 NXP Semiconductors |
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