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K32L2AX датащи(PDF) 80 Page - NXP Semiconductors |
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K32L2AX датащи(HTML) 80 Page - NXP Semiconductors |
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80 / 96 page ![]() Table 49. LPSPI master mode timing on slew rate enabled pads Num. Symbol Description Min. Max. Unit Note 1 fop Frequency of operation fperiph/2048 fperiph/2 Hz 1 2 tSPSCK SPSCK period 2 x tperiph 2048 x tperiph ns 2 3 tLead Enable lead time 1/2 — tSPSCK — 4 tLag Enable lag time 1/2 — tSPSCK — 5 tWSPSCK Clock (SPSCK) high or low time tperiph - 30 1024 x tperiph ns — 6 tSU Data setup time (inputs) 96 — ns — 7 tHI Data hold time (inputs) 0 — ns — 8 tv Data valid (after SPSCK edge) — 52 ns — 9 tHO Data hold time (outputs) 0 — ns — 10 tRI Rise time input — tperiph - 25 ns — tFI Fall time input 11 tRO Rise time output — 36 ns — tFO Fall time output 1. fperiph is the LPSPI peripheral functional clock 2. tperiph = 1/fperiph (OUTPUT) 2 8 6 7 MSB IN2 LSB IN MSB OUT2 LSB OUT 9 5 5 3 (CPOL=0) 4 11 11 10 10 SPSCK SPSCK (CPOL=1) 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. 1. If configured as an output. SS1 (OUTPUT) (OUTPUT) MOSI (OUTPUT) MISO (INPUT) BIT 6 . . . 1 BIT 6 . . . 1 Figure 22. LPSPI master mode timing (CPHA = 0) Peripheral operating requirements and behaviors 80 K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021 NXP Semiconductors |
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