K32L2AX datasheet(19/96 Pages) NXP

19 / 96 page

The crossbar switch connects bus masters and bus slaves using a crossbar switch

structure. This structure allows up to four bus masters to access different bus slaves

simultaneously, while providing arbitration among the bus masters when they access

the same slave.

2.2.3 Bit Manipulation Engine2 (BME2)

The key features of the BME2 include:

• Lightweight implementation of decorated storage for selected address spaces

• Additional access semantics encoded into the reference address

• Resides between crossbar switch slave port(s) and their associated peripheral

bridge bus controller(s)

• Two-stage pipeline design matching the AHB system bus protocol

• Combinationally passes non-decorated accesses to peripheral bridge bus

controllers

• Conversion of decorated loads and stores from processor core into atomic

readmodify- writes

• Decorated loads support unsigned bit field extracts, load-and-{set,clear} 1-bit

operations

• Decorated stores support bit field inserts, logical AND, OR, and XOR operations

• Support for byte, halfword and word-sized decorated operations

• Supports minimum signal toggling on AHB output bus to reduce power

dissipation

2.2.4 Cryptographic Acceleration Unit (CAU)

The CAU provides security encrypt/decrypt acceleration to allow users to share secure

data with external devices via a serial communication port (such as an LPUART

module). The CAU clock source is the CPU/platform clock.

There is 1 CAU module, which is connected to the Core PPB.

Overview

K32 L2A Microcontroller with 512 KB Flash and 128 KB SRAM, Rev. 3, 02/2021

NXP Semiconductors

K32L2AX датащи(PDF) 19 Page - NXP Semiconductors