BQ76PL536APAPR datasheet(12/74 Pages) TI1

12 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

www.ti.com

Electrical Characteristics (continued)

Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 85°C and VBAT = 7.2 V

to 27 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

OTP EPROM PROGRAMMING CHARACTERISTICS

VPROG

Programming voltage

VBAT ≥ 20 V

6.75

7.25

tPROG

Programming time

VBAT ≥ 20 V

(11)50

IPROG

Programming current

VBAT ≥ 20 V

(11) The write pulse is self-timed internally. VPROG should be applied for this time at a minimum.

6.6 Timing Characteristics – AC SPI Data Interface

Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 85°C and VBAT = 7.2 V

to 27 V (unless otherwise noted), see Figure 1.

PARAMETER

TEST CONDITION

MIN

NOM

MAX

UNIT

fSCLK

SCLK frequency(1)

250

1000

kHz

SCLKDC

SCLK_H duty cycle, t(HIGH) / t(SCLK) or t(LOW) / t(SCLK)

40%

60%

tCS,LEAD

CS_H lead time, CS_H low to clock

SCLK/2

tCS,LAG

CS_H lag time. Last clock to CS_H high

SCLK/2

tCS,DLY

CS_H high to CS_H low (inter-packet delay requirement)

µs

tACC

CS_H access time(2): CS_H low to SDO_H data out

125

250

tDIS

CS_H disable time(2): CS_H high to SDO_H high impedance

2.5

2.7

µs

tSU,SDI

SDI_H input-data setup time

tHD,SDI

SDI_H input-data hold time

SDO_H output-data valid time

tVALID,SDO

CL ≤ 20 pF

110

SCLK_H edge to SDO_H valid

(1)

Maximum SCLK frequency is limited by the number of bq76PL536A devices in the vertical stack. The maximum listed here may not be

realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing, and

so forth. See text for details.

(2)

Time listed is for single device.

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