BQ76PL536APAPR datasheet(51/74 Pages) TI1

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bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

7.6.25 IO_CONFIG Register (0x41)

The IO_CONFIG sets the default configuration for miscellaneous I/O features of the device.

Figure 48. IO_CONFIG Register

CRCNOFLT

Reserved

CRC_DIS

Table 21. IO_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

CRCNOFLT

This bit enables and disables detected CRC errors asserting the

FAULT pin.

0 = CRC errors cause the FAULT[CRC] bit to be set and the

FAULT pin to assert. The FAULT[CRC] bit must be reset as

described in the text.

1 = CRC errors cause the FAULT[CRC] bit to be set and the

FAULT pin is not asserted. The FAULT[CRC] bit must be reset

as described in the text.

6-1

Reserved

CRC_DIS

This bit enables and disables the automatic generation of the

CRC for the SPI communication packet. The packet size is

determined by the host as part of the read request protocol. The

CRC is checked at the deassertion of the CS pin. TI

recommends that this bit be changed using the broadcast

address (0x3f) so that all devices in a battery stack use the

same protocol.

0 = A CRC is expected, and generated as the last byte of the

packet.

1 = A CRC is not used in communications.

7.6.26 CONFIG_COV Register (0x42)

The CONFIG_COV register determines cell overvoltage threshold voltage.

Figure 49. CONFIG_COV Register

DISABLE

Reserved

COV[5]

COV[4]

COV[3]

COV[2]

COV[1]

COV[0]

Table 22. CONFIG_COV Register Field Descriptions

Bit

Field

Type

Reset

Description

DISABLE

Disables the overvoltage function when set.

0 = Overvoltage function enabled

1 = Overvoltage function disabled

Reserved

5-0

COV[n]

Configuration bits with corresponding voltage threshold

0x00 = 2 V; each binary increment adds 50 mV until 0x3c = 5 V

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