BQ76PL536APAPR datasheet(37/74 Pages) TI1

37 / 74 page

CRC_ERR

WRITE

INTERNAL DATA BUS

CONTROL, STATUS & DATA REGISTERS

FAULT _STATUSFLAGS

CRCCHECKLOGIC

SPIDE -SERIALIZER

bq76PL536A

www.ti.com

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

7.6 Register Maps

7.6.1 I/O Register Details

The bq76PL536A has 48 addressable I/O registers. These registers provide status, control, and configuration

information for the battery protection system. Reserved registers return 0x00. Unused registers should not be

written to; the results are undefined. Unused or undefined bits should be written as zeroes, and will always read

back as zeroes. Several types of registers are provided, details are in the following sections and tables.

7.6.2 Register Types

7.6.2.1 Read-Only (Group 1)

These registers contain the results of conversions, or device status information set by internal logic. The contents

are re-initialized by a device reset as a result of either POR or the RESET command. Contents of the register are

changed by either a conversion command, or when there is an internal state change (that is, a fault condition is

sensed).

7.6.2.2 Read / Write (Group 2)

The Read/Write register group modifies the operations or behavior of the device, or indicates detailed status in

the ALERT_STATUS and FAULT_STATUS registers (Figure 24). The contents are re-initialized by a device reset

as a result of either POR or the RESET command. Contents of the register are changed either by a conversion

command, or when there is an internal state change (that is, a fault condition is sensed).

Contents may also be changed by a write from the host CPU to the register. Writes may only modify a single

Packets with bad CRCs are discarded without writing the value to the register, after setting the

FAULT_STATUS[CRC] flag.

Unused or undefined bits in any register should be written as zeros, and will always read back as zeros.

Figure 24. Register Group2 Architecture

7.6.2.3 Read / Write, Initialized From EPROM (Group3)

These registers control the device configuration and functionality. The contents of the registers are initialized

from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command.

This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after

any reset, without host CPU involvement. See Figure 25 for a simplified view.

These registers may only be modified by using a special, sequential-write sequence to guard against accidental

changes. The value loaded from EPROM at reset (or by command) may be temporarily overwritten by using the

special write sequence. The temporary value is overwritten to the programmed EPROM initialization value by the

next reset or command to reload. To write to a these protected registers, first write 0x35 to SHDW_CONTROL,

immediately followed by the write to the desired register. Any intervening write cancels the special sequence.

To re-initialize the entire set of Group3 registers to the EPROM defaults, write the value 0x27 to

SHDW_CONTROL.

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