BQ76PL536APAPR datasheet(31/74 Pages) TI1

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Reg Address

Device Address

RegData

CRC

R/W

WritePacket

CS Assertion

DEV ADDR

1 byte

time

REG ADDR

WRT DATA

CRC

DEV ADDR

REG ADDR

Startofnextpacket

SDI

...

bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

7.3.6.2 Data Write Packet

When the bq76PL536A is selected (CS_S is active and the bq76PL536A has been addressed) and a write

request has been initiated, the bq76PL536A receives data through the SDI_S pin, which is connected to the

SDO_N of the lower device. For the first device in the stack, the data is input to the SDI_H pin from the host, and

transmitted up the stack on the SDI_S pin to the SDI_N pin of the next higher device. If enabled, the device

checks the CRC, which it expects as the last byte sent. If the CRC is valid, no action is taken. If the CRC is

invalid or missing, the device asserts the ALERT_S signal to the next lower device, which ripples down the stack

to the ALERT_H pin on the lowest device. The host should then take action to clear the condition. See Figure 20

and Figure 21 for details.

Unused or undefined register bits should be written as zeros.

Figure 20. WRITE Packet Format

Figure 21. WRITE Packet Detail

7.3.6.3 Broadcast Writes

The bq76PL536A supports broadcasting single register writes to all devices. A write to device address 0x3f is

recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all

registers in the stack of devices. This also permits synchronizing all ADC conversions by a firmware command

sent to the CONVERT_CTRL register as an alternative to using the CONV and DRDY pins.

7.3.6.4 Communications Packet Structure

The bq76PL536A has two primary communication modes through the SPI interface. These two modes enable

single-byte read / write and multiple data reads. All writes are single-byte; the logical address is shifted one bit

left, and the LSB = 1 for writing.

All transactions are in the form of packets comprising:

Table 4. Communication Packet Order

BYTE

DESCRIPTION

6-bit bq76PL536A slave address + R/W bit 0b0xxx xxxW

Starting data-register offset

Number of data bytes to be read (n) (omitted for writes)

#4 to 3+n

Data bytes

#4+n

CRC (omit if IO_CONFIG[CRC_DIS] = 1)

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