BQ76PL536APAPR datasheet(35/74 Pages) TI1

35 / 74 page

bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

Device Functional Modes (continued)

IO_CONTROL[TS1:TS2] bits are not modified. The host must also set these bits to zero to minimize current draw

of the thermistors themselves.

SPI communications are preserved; all registers may be read or written.

7.4.1.2 Sleep State Exit (Bit Reset)

VREG50 operation is restored.

COV, CUV, OT circuits are re-enabled.

The ADC circuitry returns to its former state. Note that there is a warm-up delay associated with the ADC enable,

the same delay as specified for enabling from a cold start.

The FAULT and ALERT registers are restored to their pre-SLEEP state. If a FAULT or ALERT condition was

present prior to SLEEP, the FAULT or ALERT pin is immediately asserted.

IC_CONTROL[TS1:TS2] should be set by the host if the OT function or temperature measurement functions are

desired.

7.5 Programming

7.5.1 Programming the EPROM Configuration Registers

The bq76PL536A has a block of OTP-EPROM that is used for configuring the operation of the bq76PL536A.

Programming of the EPROM should take place during pack/system manufacturing. A 7-V (VPP) pulse is required

on the PROG pin. The part uses an internal window comparator to check the voltage, and times the internal

pulse delivered to the EPROM array.

The user first writes the desired values to all of the equivalent Group3 protected register addresses. The desired

data is written to the appropriate address by first applying 7 V to the LDOD1(2) pins. Programming then

performed by writing to the EE_EN register (address 0x3f) with data 0x91. After a time period > 1500 µs, the 7 V

is removed. Nominally, the voltage pulse should be applied for approximately 2–3 ms. Applying the voltage for an

extended period of time may lead to device damage. The write is self-timed internally after receipt of the

command. The following flow chart (Figure 23) illustrates the procedure for programming.

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