BQ76PL536APAPR datasheet(29/74 Pages) TI1

29 / 74 page

bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

7.3.3.4 GPIO

The bq76PL536A includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit.

The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read

the IO_CONTROL[GPIO_IN] bit. A pullup (10 k

Ω–1 MΩ, typ.) is required on this pin if used as an input. If the

pullup is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent

excess current draw from the floating input. Use of a pullup is recommended in all designs to prevent an

unintentional increase in current draw.

7.3.4 Communications

7.3.4.1 SPI Communications – Device to Host

Device-to-host (D2H) mode is provided on the SPI interface pins for connection to a local host microcontroller,

logic, and so forth. D2H communications operate in voltage mode as a standard SPI interface for ease of

connection to the outside world from thebq76PL536A device. Standard TTL-compatible logic levels are

presented. All relevant SPI timing and performance parameters are met by this interface.

The host interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. The SPI clock is normally low; data

changes on rising edges, and is sampled on the falling edge. All transfers are MSB-first.

The pins of the base IC (only) in a stack should have the SCLK_H and SDI_H pins terminated with pullups to

minimize current draw of the part if the host ever enters a state where the pins are not driven, that is, held in the

high-impedance state by the host. In non-base devices, the _H pins are forced to be all outputs driven low when

the HSEL pin is high. In non-base devices, all _H pins should remain unconnected.

The CS_H has a pullup resistor of approximately 100 k

Ω. SDO_H is a 3-state output and is terminated with a

weak pullup.

NOTE

Designer Note: When VBAT is at or below the UVLO trip point voltage, the internal LDO

which supplies the xxxx_H host SPI communications pins (VLODx) begins to fall out of

regulation. The output high voltage on the xxxx_H pins falls off with the LDO voltage in an

approximately linear manner until at the POR voltage trip point where it is reduced to

approximately 3.5 V. This action is not tested in production.

7.3.5 Device-to-Device Vertical Bus (VBUS) Interface

Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides

common-mode voltage isolation between successive bq76PL536As. This vertical bus (VBUS) is found on the _N

and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV and

DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed.

The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of

bq76PL536As. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped; _S

always points South, and _N always point North. The _S and _N pins are interconnected to the pin with the

same name, but opposite suffix. All pins operate within the voltages present at the BAT and VSS pins.

WARNING

These pins may be several hundred volts above system ground, depending on

their position in the stack.

NOTE

Designer Note: North (_N) pins of the top, most-positive device in the stack should be

connected to the BAT1(2) pins of the device for correct operation of the string. South (_S)

pins of the lowest, most-negative device in the stack should be connected to VSS of the

device.

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