BQ76PL536APAPR datasheet(44/74 Pages) TI1

44 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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7.6.10 COV_FAULT Register (0x22)

Figure 33. COV_FAULT Register

Reserved

OV[6]

OV[5]

OV[4]

OV[3]

OV[2]

OV[1]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. COV_FAULT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

5-0

OV[6]..[1]

These

bits

indicate

which

cell

caused

the

DEVICE_STATUS[COV] flag to be set.

0 = Cell[n] does not have an overvoltage fault (default).

1 = Cell[n] does have an overvoltage fault.

7.6.11 CUV_FAULT Register (0x23)

Figure 34. CUV_FAULT Register

Reserved

UV[6]

UV[5]

UV[4]

UV[3]

UV[2]

UV[1]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. CUV_FAULT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

Reserved

5-0

UV[6]..[1]

These

bits

indicate

which

cell

caused

the

DEVICE_STATUS[CUV] flag to be set.

0 = Cell[n] does not have an undervoltage fault (default).

1 = Cell[n] does have an undervoltage fault.

7.6.12 PARITY_H Register (0x24) (PRESULT_A (R/O))

The PRESULT_A register holds the parity result bits for the first eight Group3 protected registers.

Figure 35. PARITY_H Register

OTT

OTV

CUVT

CUVV

COVT

COVV

FUNC

7.6.13 PARITY_H Register (0x25) (PRESULT_B (R/O))

The PRESULT_B register holds the parity result bits for the second eight Group3 protected registers.

Figure 36. PARITY_H Register

Reserved

USER4

USER3

USER2

USER1

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