BQ76PL536APAPR datasheet(42/74 Pages) TI1

42 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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7.6.8 ALERT_STATUS Register (0x20)

The ALERT_STATUS register provides information about the source of the ALERT signal. The host must clear

each alert flag by writing a 1 to the bit that is set. The exception is bit 4, which may be written 1 or 0 as needed

to implement self-test of the IC stack and wiring.

Figure 31. ALERT_STATUS Register

PARITY

ECC_ERR

FORCE

TSD

SLEEP

OT2

OT1

Table 7. ALERT_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

This bit indicates that the ADDR[0]…[5] bits have been written to

valid

address.

This

bit

inverted

copy

the

ADDRESS_CONTROL[AR] bit. It is not cleared until an address

has been programmed in ADDRESS_CONTROL and a 1

followed by a 0 (two writes) is written to the bit.

0 = Address has been assigned.

1 = Address has not been assigned (default at RESET).

PARITY

This bit is used to validate the contents of the protected Group3

registers.

0 = Group3 protected register(s) contents are valid.

1 = Group3 protected register(s) contents are invalid. Group3

registers should be refreshed from OTP or directly written from

the host.

ECC_ERR

This bit is used to validate the OTP register blocks.

0 = No double-bit errors (a corrected one-bit error may/may not

exist)

1 = An uncorrectable error has been detected in the OTP-

EPROM register bank. OTP-EPROM register(s) are not valid.

FORCE

This bit asserts the ALERT signal. It can be used to verify

correct operation and connectivity of the ALERT as a part of

system self-test.

0 = De-assert ALERT (default)

1 = Assert the ALERT signal.

TSD

This bit indicates thermal shutdown is active.

0 = Thermal shutdown is inactive (default).

1 = Die temperature has exceeded TSD.

SLEEP

This bit indicates SLEEP mode was activated. This bit is only set

when SLEEP is first activated; no continuous ALERT or SLEEP

status is indicated after the host resets the bit, even if the

IO_CTRL[SLEEP] bit remains true. (See IO_CTRL register for

details.)

0 = Normal operation

1 = SLEEP mode was activated.

OT2

This bit indicates an overtemperature fault has been detected

via TS2.

0 = Temperature is lower than or equal to the VOT2 (or input

disabled by IO_CONTROL[TS2] = 0).

1 = Temperature is higher than VOT2.

OT1

This bit indicates an overtemperature fault has been detected

via TS1.

0 = Temperature is lower than or equal to the VOT1 (or input

disabled by IO_CONTROL[TS1] = 0).

1 = Temperature is higher than VOT1.

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