BQ76PL536APAPR datasheet(22/74 Pages) TI1

22 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

www.ti.com

7.3.1.8 Secondary Protection

The bq76PL536A integrates dedicated overvoltage and undervoltage fault detection for each cell and two

overtemperature fault detection inputs for each device. The protection circuits use a separate band-gap reference

from the ADC system and operate independently. The protector also uses separate I/O pins from the main

communications bus, and therefore is capable of signaling faults in hardware without intervention from the host

CPU.

7.3.1.8.1

Protector Functionality

When a fault state is detected, the respective fault flag in the FAULT_STATUS or ALERT_STATUS registers is

set. All flags in the FAULT and ALERT registers are then ORed into the DEVICE_STATUS FAULT and ALERT

bits. The FAULT and ALERT bits in DEVICE_STATUS in turn cause the hardware FAULT_S or ALERT_S pin to

be set. The bits in DEVICE_STATUS and the hardware pins are latched until reset by the host via SPI command,

ensuring that the host CPU does not miss an event.

A separate timer is provided for each fault source (cell overvoltage, cell undervoltage, overtemperature) to

prevent false alarms. Each timer is programmable from 100 µs to more than 3 s. The timers may also be

disabled, which causes fault conditions to be sensed immediately and not latched.

The clearing of the FAULT or ALERT flag (and pin) occurs when the respective flag is written to a 1, which also

restarts the respective fault timer. This also clears the FAULT_S (_H) or ALERT_S (_H) pin. If the actual fault

remains present, the FAULT (ALERT) pin is again asserted at the expiration of the timer. This cycle repeats until

the cause of the fault is removed.

On exit from the SLEEP state, the COV, CUV, and OT fault comparators are disabled for approximately 200 µs

to allow internal circuitry to stabilize and prevent false error condition detection.

7.3.1.8.1.1

Using the Protector Functions With 3-5 Cells

The OV/UV condition can be ignored for unused channels by setting the FUNCTION_CONFIG[CNx] bits to the

maximum number of cells connected to the device. If fewer than 6 cells are configured, the corresponding OV/UV

faults are ignored. For example, if the FUNCTION_CONFIG bits are set to xxxx 1000, then the OV/UV

comparators are disabled for cells 5 and 6. Correct setting of this register prevents spurious false alarms.

Submit Documentation Feedback

Product Folder Links: bq76PL536A

BQ76PL536APAPR датащи(PDF) 22 Page - Texas Instruments