BQ76PL536APAPR datasheet(38/74 Pages) TI1

38 / 74 page

PROTECTED

EPROM

ERRORCHECK /

CORRECT (ECC) LOGIC

LOAD

PROGRAM

PARITY

ECC_COR

ECC_ERR

REFRESH

POR

REFRESH-PROTECT KEY

VOLTAGE &

TIMINGCONTROL

PGM-PROTECT KEY

WRITE-PROTECTKEY

WRITE

LOADsignalevaluates

ECCsyndromebits

KEY requiressequenced

writetounlockfunction

PARITY LOGIC

CHECKBITS

INTERNAL DATA BUS

SYNDROMECHECKER / GENERATOR

Cn+1...

REGISTERCONTROL & STATUSBITS

STATUSFLAGS

Nodirectaccesstothisregister.

1 biterror

2+ biterrors

CRCCHECKLOGIC

SPIDE-SERIALIZER

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

www.ti.com

These registers are protected further against corruption by a ninth parity bit that is automatically updated when

the register is written using even parity. If the contents of the register ever become corrupted, the bad parity

causes the ALERT_STATUS[PARITY] bit to become set, alerting the host CPU of the problem.

The EPROM-stored constants are programmed by writing the values to the register(s), then applying the

programming voltage to the LDODx pins, then issuing the EPROM_WRITE command to register E_EN. All

Group3 registers are programmed simultaneously, and this operation can only be performed once to the one-

time-programmable (OTP) memory cells. The process is not reversible.

Figure 25. Protected Register Group3 Architecture, Simplified View

7.6.2.4 Error Checking and Correcting (ECC) EPROM

The EPROM used to initialize this group is also protected by error-check-and-correct (ECC) logic. The ECC bits

provide a highly reliable storage solution in the presence of external disturbances. This feature cannot be

disabled by user action. Implementation is fully self-contained and automatic and requires no special

computations or provisioning by the user.

When the Group3 contents are permanently written to EPROM, an additional array of hidden ECC-OTP cells is

also automatically programmed. The ECC logic implements a Hamming code that automatically corrects all

single-bit errors in the EPROM array, and senses additional multi-bit errors. If any corrections are made, the

DEVICE_STATUS[ECC_COR] flag bit is set. If any multi-bit errors are sensed, the ALERT_STATUS[ECC_ERR]

flag is set. The corrective action or detection is performed anytime the contents of EPROM are loaded into the

registers – POR, RESET, or by REFRESH command. Note: The ECC_COR and ECC_ERR bits may glitch

during OTP-EPROM writes; this is normal. If this occurs, reset the tripped bit; it should remain cleared.

When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for

bottom stack device) line is activated, and the ALERT_STATUS register returns the ECC_ERR and/or I_FAULT

bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults

in this state.

EPROM bits are shipped from the factory set to 0, and must be programmed to the 1 state as required.

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