BQ76PL536APAPR datasheet(34/74 Pages) TI1

34 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

www.ti.com

Once

the

address

written,

the

ADDRESS_CONTROL[AR]

bit

set

which

copied

the

DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow

(asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new

address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack.

If a device loses its address through a POR or it is replaced then this device will be the highest logical device in

the stack able to be addressed (0x00) as its CS_N will be disabled and the addressing process is required for

this and higher devices.

7.3.8 Changes and Enhancements for bq76PL536A

•

Improved power management during CRC faults – Configuration bit IO_CONFIG[CRCNOFLT] (bit7) was

added to disable CRC fault from asserting the FAULT pin. This feature is useful under very low-power

operating conditions.

•

ADC accuracy improvements – The conversion timing is now fixed at 6 µs, offering improved accuracy over

the original bq76PL536.

•

Improved ADC automatic mode functionality, allowing optimized and fully automatic internal power

management (ADC_CTRL[ADC_ON] = 0) during normal operation at sample rates (time between

conversions) > 10 ms.

•

Pin DRDY logic now indicates conversion status of all devices in the system.

•

Improved VBUS communications reduce noise, enhance drive levels and hysteresis to improve battery stack

communications, and eliminate eight external components or more. Support for longer distances between ICs

and/or higher speeds for implementing large battery stack sizes.

•

Improved flowchart for device addressing provided in data sheet.

Spacer

7.4 Device Functional Modes

7.4.1 SLEEP Functionality

The bq76PL536A provides the host a mechanism to put the part into a low-power sleep state by setting the

IO_CONTROL[SLEEP] bit. When this bit is set/reset, the following actions occur as stated in the following

paragraphs.

7.4.1.1 SLEEP State Entry (Bit Set)

If a conversion is in progress, the device waits for it to complete, then sets DRDY true (high).

The device sets the ALERT_STATUS[SLEEP] bit, which in turn causes the ALERT pin to be asserted.

The device gates off all other sources of FAULT or ALERT except ALERT[SLEEP]. The existing state of the

FAULT and ALERT registers is preserved. The host should service and reset the ALERT generated by the

SLEEP bit being set to minimize SLEEP state current draw by writing a 1 to ALERT[SLEEP] followed by a 0 to

ALERT[SLEEP]. The ALERT North-South signal chain can draw up to approximately 1 mA of current when

active, so this ALERT source should be cleared prior to the host entering the SLEEP state of its own. This

signaling is provided to notify the host that the unmonitored/unprotected state is being entered.

The REG50 LDO is shut down and the output is allowed to float. The ADC, its reference, and clocks are

disabled. The COV, CUV, and OT circuits are disabled, and their band-gap reference shut off.

CAUTION

The SLEEP State effectively removes protection and monitoring from the cells; the

designer should take the necessary design steps and verifications to ensure the cells

cannot be put into an unsafe condition by other parts of the system or usage

characteristics.

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