BQ76PL536APAPR datasheet(40/74 Pages) TI1

40 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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7.6.3 Register Details

7.6.3.1 DEVICE_STATUS Register (0x00)

The STATUS register provides information about the current state of the bq76PL536A.

Figure 26. DEVICE_STATUS Register

ADDR_RQST

FAULT

ALERT

Reserved

ECC_COR

UVLO

CBT

DRDY

Table 6. DEVICE_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

ADDR_RQST

This bit is written to indicate that the ADDR[0]…[5] bits have

been written to the correct address. This bit is a copy of in the

ADDRESS_CONTROL[AR] bit.

0 = Address has not been assigned

1 = Address has been assigned

FAULT

This bit indicates that this bq76PL536A has detected a condition

causing the FAULT signal to become asserted.

0 = No FAULT exists

1 = A FAULT exists. Read FAULT_STATUS to determine the

cause.

ALERT

This bit indicates that this bq76PL536A has detected a condition

causing the ALERT pin to become asserted.

0 = No ALERT exists

1 = An ALERT exists. Read ALERT_STATUS to determine the

cause.

Reserved

ECC_COR

This bit indicates a one-bit error has been detected and

corrected in the EPROM.

0 = No errors are detected in the EPROM

1 = A one-bit (single bit) error has been detected and corrected

by on-chip logic.

UVLO

This bit indicates the device VBAT has fallen below the

undervoltage lockout trip point. Some device operations are not

valid in this condition.

0 = Normal operation

1 = UVLO trip point reached, device operation is not ensured.

CBT

This bit indicates the cell balance timer is running.

0 = The cell balance timer is has not started or has expired.

1 = The cell balance timer is running.

DRDY

This bit indicates the data is ready to read (no conversions

active).

0 = There are conversions running.

1 = There are no conversions running.

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