BQ76PL536APAPR datasheet(24/74 Pages) TI1

24 / 74 page

REG50

RTH

REG50

TS+

TS–

ALERT[OTn]

PIN BOUNDARY

To ADC Mux

–

Delay Filter

COMPARATOR

CONFIG_OT[] Selector

CONFIG

_OTT[]

CONFIG _OT[]?0

VSS

–

PROTECTOR

REFERENCE

5V LDO

(User)

To COV-CUV Circuits

VBAT

IO_CONTROL[TS]n

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

www.ti.com

7.3.1.10 Cell Undervoltage Fault Detection (CUV)

Cell undervoltage detection operates in a similar manner to the COV protection. When the voltage across a cell

falls below the programmed CUV threshold (CONFIG_CUV) for a period of time greater than CUVT

(CONFIG_CUVT), the CUV_FAULT flag for that cell is set. The bits in CUV_FAULT are then ORed into the

FAULT[CUV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H)

pin also to be asserted. The CUV flag is latched unless CUVT is programmed to 0, in which case the flag follows

the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the

FAULT flag, first remove the source of the fault (for example, the overvoltage condition) and then write a 1 to

FAULT[CUV], followed by a 0 to FAULT[CUV].

7.3.1.11 Overtemperature Detection

When the temperature input TS1 or TS2 exceeds the programmed OT1 or OT2 threshold (CONFIG_OT) for a

period of time greater than OTT (CONFIG_OTT) the ALERT_STATUS[OT1, OT2] flag is set (Figure 17). The

ALERT flags are then ORed into the DEVICE_STATUS[ALERT] flag, and the ALERT_S (_H) pin is also

asserted. The OT flag is latched unless OTT is programmed to 0, in which case the flag follows the fault

condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT

flag, first remove the source of the alert (for example, the overtemperature condition) and then write a 1 to

ALERT[OTn], followed by a 0 to FAULT[OTn].

Figure 17. Simplified Overtemperature Detection Schematic

As shown in Figure 17, the OT thresholds are detectable in 11 steps representing approximately 5°C divisions

when a thermistor and gain/offset setting resistors are chosen using the formula in the External Temperature

Sensor Support (TS1+, TS1– and TS2+, TS2–) section. A DISABLED setting is also available. This results in an

adjustment range from approximately 40°C to 90°C, but the range center can be moved by modifying the RT

value. The steps are spaced in a non-linear fashion to correspond to typical thermistor response curves. Typical

accuracy of a few degrees C or better can be achieved (with no additional calibration requirements) by careful

selection of the thermistor and resistors.

Each input sensor can be adjusted independently via separate registers CONFIG_OT1 and CONFIG_OT2. The

two temperature set points share a common filter delay set in the CONFIG_OTT register. A setting of 0 in the

CONFIG_OTT register causes the fault sensing to be both instantaneous and not latched. All other settings

provide a latched ALERT state.

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