BQ76PL536APAPR datasheet(20/74 Pages) TI1

20 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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Feature Description (continued)

7.3.1.6 ADC Band-Gap Voltage Reference

The ADC and protection subsystems use separate and independent internal voltage references. The ADC band

gap (VREF) is nominally 2.5 V. The reference is temperature-compensated and stable.

The internal reference is brought out to the VREF pin for bypassing. A high quality 10-

μF capacitor should be

connected between the VREF and AGND pins, in very close physical proximity to the device pins, using short

track lengths to minimize the effects of track inductance on signal quality. The AGND pin should be connected to

VSS. Device VSS connections should be brought to a single point close to the IC to minimize layout-induced

errors. The device tab should also be connected to this point, and is a convenient common VSS location. The

internal VREF should not be used externally to the device by user circuits.

7.3.1.7 Conversion Control

7.3.1.7.1

Convert Start

Two methods are available to start a conversion cycle. The CONV_H pin may be asserted, or firmware may set

the CONVERT_CTRL[CONV] bit.

7.3.1.7.1.1

Hardware Start

A single interface pin (CONV_H) is used for conversion-start control by the host. A conversion cycle is started by

a hardware signal when CONV_H is transitioned low-to-high by the host. The host should hold this state until the

conversion cycle is complete to avoid erroneous edges causing a conversion start when the present conversion

is not complete. The signal is simultaneously sent to the higher device in the stack by the assertion of the

CONV_N signal. The bq76PL536A automatically sequences through the series of measurements enabled via the

ADC_CONTROL register after a convert-start signal is received from either the register bit or the hardware pin.

If the CONV_H pin is not used in the design, this pin must be maintained in a default low state (approximately 0

V) to allow use of the ADC_CONVERT[CONV] bit to trigger ADC conversions. If the CONV pin is kept high, the

ADC_CONVERT[CONV] bit does not function, and device current consumption is increased by the signaling

current, approximately 900 µA. If the CONV_H pin is not used by the user’s design, the pin may be left floating;

the internal current sink to VSS maintains proper bias.

7.3.1.7.1.2

Firmware Start

The CONVERT_CTRL[CONV] bit is also used to initiate a conversion by writing a 1 to the bit, which

automatically resets at the end of a conversion cycle. The bit may only be written to 1; the IC always resets the

bit to 0. The BROADCAST form of the packet is recommended to start all device conversions simultaneously.

NOTE

Designer Note: The external CONV_H (CONV_S) pin must be held in the de-asserted (=0)

state to allow the CONV register bit to initiate conversions. An internal pulldown is

provided on the pin to maintain this state.

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