BQ76PL536APAPR datasheet(63/74 Pages) TI1

63 / 74 page

bq76PL536A

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SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

9 Power Supply Recommendations

9.1 Power Supply Decoupling

The LDOA, LDOD1, LDOD2 and REG50 pins all require a 2.2-µF ceramic capacitor to be placed as closely as

possible to the respective pins to optimize stability. The bq76PL536A requires a power supply with between 7.2

V to 27 V inputs. When fewer than six cells are used, see Figure 13 for details.

10 Layout

10.1 Layout Guidelines

For typical applications, the following guidelines and practices should be followed closely:

•

VREF and AGND pins require a high-quality 10-µF capacitor be connected between them, in very close

physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on

signal quality.

–

The AGND pin should be connected to VSS. Device VSS connections should be brought to a single point

close to the IC to minimize layout-induced errors. The device tab should also be connected to this point,

and is a convenient common VSS location. The internal VREF should not be used externally to the device

by user circuits.

•

The internal analog supply should be bypassed at the LDOA pin with a good-quality, low-ESR, 2.2-µF

ceramic capacitor.

NOTE

Because the LDODx inputs are pulled to approximately 7 V during programming,

programming time MUST be < 50 ms.

•

The bq76PL536A has a low-dropout (LDO) regulator provided to power the thermistors and other external

circuitry. The input for this regulator is VBAT. The output of REG50 is typically 5 V. A minimum 2.2-µF

capacitor is required for stable operation. The output is internally current-limited and is reduced to near zero,

if excess current is drawn, causing die temperatures to rise to unacceptable levels. The 2.2-µF output

capacitor is required whether REG50 is used in the design or not. REG50 is disabled in SLEEP mode, may

be turned off under thermal-shutdown conditions, and therefore should not be used as a pull-up source for

terminating device pins where required.

•

The bq76PL536A includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT]

bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and

then read the IO_CONTROL[GPIO_IN] bit. A pull-up (10 k

Ω–1 MΩ, typical) is required on this pin if used as

an input. If the pull-up is not included in the design, system firmware must program a 0 in

IO_CONTROL[GPIO_OUT] to prevent excess current draw from the floating input. Use of a pull-up is

recommended in all designs to prevent an unintentional increase in current draw.

•

Device-to-device (D2D) communications makes use of a unique, current-mode interface which provides

common-mode voltage isolation between successive bq76PL536As. This vertical bus (VBUS) is found on the

_N and corresponding _S pins. It provides high-speed I/O for both the SPI bus and the direct I/O pins CONV

and DRDY. The current-mode interface minimizes the effects of wiring capacitance on the interface speed.

The _S (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of

bq76PL536As. The _N (North facing) pins connect to the next-higher device. The pins cannot be swapped;

_S always points South, and _N always point North. The _S and _N pins are interconnected to the pin with

the same name, but opposite suffix.

–

All pins operate within the voltages present at the BAT and VSS pins.

–

The maximum SCLK frequency is limited by the number of devices in the vertical stack and other factors.

Each device imposes an approximately 30-ns delay on the round trip communications speed; that is, from

SCLK rise time (an input to all devices) to the SDO pin transition time requires approximately 30 ns per

device. The designer must add to this the delay caused by the PCB trace (in turn determined by the

material and layout), any connectors in series with the connection, and any other wiring or cabling

between devices in the system.

•

When designing the layout, several considerations need to be taken into account.

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