BQ76PL536APAPR datasheet(56/74 Pages) TI1

56 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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8.2.1 Design Requirements

For this design example, use the parameters listed in Table 26.

Table 26. Design Parameters

PARAMETER

DESCRIPTION

EXAMPLE VALUE

UNIT

CEMI

EMI Capacitor

3300

CFILT

Filter Capacitor

0.1

µF

CIN

Input Capacitor

0.1

µF

CREGOUT

REGOUT Capacitor

2.2 (minimum)

µF

CVDDA_1

Internal analog 5-V LDO bypass connection 1

2.2

µF

CVDDA_2

Internal analog 5-V LDO bypass connection 2

0.2

µF

Capacitor for internal digital 5-V LDO bypass

CVDD_D_1

2.2

µF

connection 1

Capacitor for internal digital 5-V LDO bypass

CVDD_D_2

0.2

µF

connection 2

CVREF

VREF Capacitor

µF

LEMI

EMI Ferrite Resistor

500

RBAL

Balance Resistor

RIN

Input Resistor

RPULL1-RPULL3

Pullup Resistors for digital open-drain I/O

Pullup Resistors for general-purpose (differential)

RPULL4-RPULL5

analog input (GPAI), connect to VSS if unused

8.2.2 Detailed Design Procedure

Use the following for the procedure for the recommended front-end circuit:

1. Select the RC filter closest to the cell for filter requirements. Additional poles can be added with a differential

capacitor to get very low fc.

2. ADC is calibrated to use RIN = 1 kΩ and CIN = 0.1 µF.

3. Select Zener diode for lowest possible reverse leakage.

4. A balance FET gate-protection diode is required (available internally).

5. Select the capacitors for LDO Filters according to Table 26.

–

LDO1 and LDO2 require a 2.2-µF ceramic capacitor for stability. These pins are tied together internally.

Tie LDO1 to LDOD2 externally.

6. For pullup supply, the following information applies:

(a) REG50 turns off in SLEEP mode

(b) Use LDOD for pullups in normal use

(d) Connect GPAI+ and GPA– to VSS if unused

7. Select low impedance and polarized connectors. Numbered or colored connectors are also good options.

8. Select the input Zener TVS so that it clamps below 5.6 Vdc, with low-leakage current, and must be able to

handle transient surge energy

9. Select capacitors based on temperature and environment with voltages well above the operating voltage

10. Select balancing MOSFETs according to the following:

(a) Low turn on threshold voltage (must turn on with the lowest cell voltage)

(b) Drain-to-source voltage and gate-to-source voltage

(d) Current based on selected bleed resistor value

11. Select the Bleed Resistor according to the following:

(a) Value based on desired current

(b) Wattage to handle the current and temperature rise such as 4.2 V × 47 = 0.089 A

∴ 0.37 W)

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