PIC16C71 datasheet(20/337 Pages) MICROCHIP

20 / 337 page

PIC16C6X

DS30234D-page 20

FIGURE 4-4:

PIC16C66/67 PROGRAM

MEMORY MAP AND STACK

4.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

RP1:RP0 (STATUS<6:5>)

= 00

→ Bank0

= 01

→ Bank1

= 10

→ Bank2

= 11

→ Bank3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access.

4.2.1

GENERAL PURPOSE REGISTERS

These registers are accessed either directly or indi-

rectly

through

the

File

Select

(FSR)

(Section 4.5).

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

PC<12:0>

Stack Level 1

Stack Level 8

CALL, RETURN

RETFIE, RETLW

0000h

0004h

0FFFh

1000h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

0005h

Reset Vector

Peripheral Interrupt Vector

••

•

07FFh

0800h

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

17FFh

1800h

1FFFh

For the PIC16C61, general purpose register locations

8Ch-AFh of Bank 1 are not physically implemented.

These locations are mapped into 0Ch-2Fh of Bank 0.

FIGURE 4-5:

PIC16C61 REGISTER FILE

MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

2Fh

30h

7Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

AFh

B0h

FFh

Bank 0

Bank 1

INDF(1)

TMR0

OPTION

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

General

Purpose

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

Mapped

in Bank 0(2)

Unimplemented data memory location; read as '0'.

Note 1:

Not a physical register.

These locations are unimplemented in

Bank 1. Any access to these locations will

access the corresponding Bank 0 register.

File Address

PIC16C71 датащи(PDF) 20 Page - Microchip Technology

PIC16C71 датащи(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL