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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16C71 датащи(PDF) 38 Page - Microchip Technology |
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PIC16C71 датащи(HTML) 38 Page - Microchip Technology |
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38 / 337 page  PIC16C6X DS30234D-page 38 © 1997 Microchip Technology Inc. 4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the peripheral interrupts. Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch) RW-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit7 bit0 bit 7-6: Reserved: Always maintain these bits clear. bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt |
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