PIC16C71 datasheet(72/337 Pages) MICROCHIP

72 / 337 page

PIC16C6X

DS30234D-page 72

8.1

Timer1 Operation in Timer Mode

Timer mode is selected by clearing bit TMR1CS

(T1CON<1>). In this mode, the input clock to the timer

is Fosc/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

8.2

Timer1 Operation in Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode the timer increments on every rising edge of

clock input on T1OSI when enable bit T1OSCEN is set

or pin with T1CKI when bit T1OSCEN is cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The pres-

caler stage is an asynchronous ripple counter.

In this conﬁguration, during SLEEP mode, Timer1 will

not increment even if an external clock is present, since

the synchronization circuit is shut off. The prescaler,

however, will continue to increment.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Note:

The T1OSI function is multiplexed to differ-

ent pins, depending on the device. See the

pinout descriptions to see which pin has

the T1OSI function.

8.2.1

EXTERNAL CLOCK INPUT TIMING FOR

SYNCHRONIZED COUNTER MODE

When an external clock input is used for Timer1 in syn-

chronized counter mode, it must meet certain require-

ments. The external clock requirement is due to

internal phase clock (Tosc) synchronization. Also, there

is a delay in the actual incrementing of TMR1 after syn-

chronization.

When the prescaler is 1:1, the external clock input is

the same as the prescaler output. The synchronization

of T1CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T1CKI to be high for at least 2Tosc (and

a small RC delay of 20 ns) and low for at least 2Tosc

(and a small RC delay of 20 ns). Refer to appropriate

electrical speciﬁcation section, parameters 45, 46, and

47.

When a prescaler other than 1:1 is used, the external

clock input is divided by the asynchronous ripple-

counter type prescaler so that the prescaler output is

symmetrical. In order for the external clock to meet the

sampling requirement, the ripple counter must be taken

into account. Therefore, it is necessary for T1CKI to

have a period of at least 4Tosc (and a small RC delay

of 40 ns) divided by the prescaler value. The only

requirement on T1CKI high and low time is that they do

not violate the minimum pulse width requirements of

10 ns). Refer to applicable electrical speciﬁcation sec-

tion, parameters 40, 42, 45, 46, and 47.

FIGURE 8-2:

TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP input

T1OSCEN

Enable

Oscillator(1)

TMR1IF

Overﬂow

Interrupt

Fosc/4

Internal

Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

clock input

T1OSO(2)

T1OSI(2)

TMR1

ﬂag bit

(3)

Note 1:

When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

See pinouts for pins with T1OSO and T1OSI functions.

For the PIC16C62/64/65, the Schmitt Trigger is not implemented in external clock mode.

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