PIC16C71 datasheet(65/337 Pages) MICROCHIP

65 / 337 page

DS30234D-page 65

PIC16C6X

7.0

TIMER0 MODULE

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Read and write capability

- Interrupt on overﬂow from FFh to 00h

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 7-1 is a simpliﬁed block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two instruction cycles (Figure 7-2 and

Figure 7-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS. In this

mode, Timer0 will increment either on every rising or

falling edge of pin RA4/T0CKI. The incrementing edge

is determined by the source edge select bit T0SE

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

(OPTION<4>). Clearing bit T0SE selects the rising

edge. Restrictions on the external clock input are dis-

cussed in detail in Section 7.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. The pres-

caler assignment is controlled in software by control bit

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4, ...,

1:256 are selectable. Section 7.3 details the operation

of the prescaler.

7.1

TMR0 Interrupt

The TMR0 interrupt is generated when the register

(TMR0) overﬂows from FFh to 00h. This overﬂow sets

interrupt ﬂag bit T0IF (INTCON<2>). The interrupt can

be masked by clearing enable bit T0IE (INTCON<5>).

Flag bit T0IF must be cleared in software by the TImer0

interrupt service routine before re-enabling this inter-

rupt. The TMR0 interrupt cannot wake the processor

from SLEEP since the timer is shut off during SLEEP.

Figure 7-4 displays the Timer0 interrupt timing.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM

FIGURE 7-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER

Note 1:

Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).

The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0 reg

PSout

(2 cycle delay)

PSout

Data bus

Set bit T0IF

on overﬂow

PSA

PS2, PS1, PS0

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

T0+1

T0+2

NT0

NT0+1

NT0+2

MOVWF TMR0

MOVF TMR0,W

Write TMR0

executed

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0 + 2

Instruction

Executed

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