PIC16C71 datasheet(75/337 Pages) MICROCHIP

75 / 337 page

DS30234D-page 75

PIC16C6X

9.0

TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

postscaler. It is especially suitable as PWM time-base

for PWM mode of CCP module(s). TMR2 is a readable

and writable register, and is cleared on any device

reset.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4

1:16,

selected

control

bits

T2CKPS1:T2CKPS0 (T2CON<1:0>).

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is ini-

tialized to FFh upon reset.

The match output of the TMR2 register goes through a

4-bit postscaler (which gives a 1:1 to 1:16 scaling,

inclusive) to generate a TMR2 interrupt (latched in ﬂag

bit TMR2IF (PIR1<1>)).

The Timer2 module can be shut off by clearing control

bit TMR2ON (T2CON<2>) to minimize power con-

sumption.

Figure 9-2 shows the Timer2 control register. T2CON is

cleared upon reset which initializes Timer2 as shut off

with the prescaler and postscaler at a 1:1 value.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

9.1

Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (POR, BOR, MCLR Reset, or

WDT Reset).

TMR2 is not cleared when T2CON is written.

9.2

Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

Synchronous Serial Port module which optionally uses

it to generate shift clock.

FIGURE 9-1:

TIMER2 BLOCK DIAGRAM

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

Comparator

TMR2

Sets

interrupt

TMR2IF

TMR2 reg

output(1)

Reset

Postscaler

Prescaler

PR2 reg

Fosc/4

1:1 to 1:16

1:1, 1:4, 1:16

TMR2

ﬂag bit,

Note

TMR2 register output can be software selected by

the SSP Module as a baud clock.

FIGURE 9-2:

T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0

R/W-0

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON

T2CKPS1 T2CKPS0

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

Unimplemented: Read as '0'

bit 6-3:

TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000

= 1:1 postscale

0001

= 1:2 postscale

•

1111

= 1:16 postscale

bit 2:

TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0:

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

= 1:1 prescale

= 1:4 prescale

= 1:16 prescale

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