PIC16C71 datasheet(79/337 Pages) MICROCHIP

79 / 337 page

DS30234D-page 79

PIC16C6X

10.1.4

CCP PRESCALER

There are four prescaler settings, speciﬁed by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore the ﬁrst capture may be from

a non-zero prescaler. Example 10-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

CCP1CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS ; Load the W reg with

; the new prescaler

; mode value and CCP ON

MOVWF

CCP1CON

; Load CCP1CON with

; this value

10.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time interrupt ﬂag bit CCP1IF is set.

FIGURE 10-3: COMPARE MODE

OPERATION BLOCK

DIAGRAM

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special event trigger will reset Timer1, but not

Special Event Trigger

Set CCP1IF

PIR1<2>

match

RC2/CCP1

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

set interrupt ﬂag bit TMR1IF (PIR1<0>).

10.2.1

CCP PIN CONFIGURATION

The user must conﬁgure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

10.2.1

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

10.2.2

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt is chosen, the

CCP1 pin is not affected. Only a CCP interrupt is gen-

erated (if enabled).

10.2.3

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 and CCP2

resets the TMR1 register pair. This allows the

CCPR1H:CCPR1L and CCPR2H:CCPR2L registers to

effectively be 16-bit programmable period register(s)

for Timer1.

For compatibility issues, the special event trigger out-

put of CCP1 (PIC16C72) and CCP2 (all other

PIC16C7X devices) also starts an A/D conversion.

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

Note:

The “special

event

trigger” from

the

CCP1and CCP2 modules will not set inter-

rupt ﬂag bit TMR1IF (PIR1<0>).

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