PIC16C71 datasheet(44/337 Pages) MICROCHIP

44 / 337 page

PIC16C6X

DS30234D-page 44

FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch)

R/W-0

R-0

R/W-0

PSPIF

—

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

PSPIF: Parallel Slave Port Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write operation has taken place

bit 6:

Reserved: Always maintain this bit clear.

bit 5:

RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty

bit 4:

TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full

bit 3:

SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2:

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0:

TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂow occurred (must be cleared in software)

0 = No TMR1 register overﬂow occurred

Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the

global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to

enabling an interrupt.

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