PIC16C71 datasheet(91/337 Pages) MICROCHIP

91 / 337 page

DS30234D-page 91

PIC16C6X

11.3.1

SSP MODULE IN SPI MODE FOR

PIC16C66/67

The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. To

accomplish communication, typically three pins are

used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL

Additionally a fourth pin may be used when in a slave

mode of operation:

• Slave Select (SS) RA5/SS

When initializing the SPI, several options need to be

speciﬁed. This is done by programming the appropriate

control bits in the SSPCON register (SSPCON<5:0>)

and SSPSTAT<7:6>. These control bits allow the fol-

lowing to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

The SSP consists of a transmit/receive Shift Register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb ﬁrst. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the 8-bits of data

have been received, that byte is moved to the SSPBUF

Then

the

buffer

full

detect

bit

(SSPSTAT<0>) and interrupt ﬂag bit SSPIF (PIR1<3>)

are set. This double buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored, and the write collision detect bit WCOL

(SSPCON<7>) will be set. User software must clear the

WCOL bit so that it can be determined if the following

write(s) to the SSPBUF register completed success-

fully. When the application software is expecting to

receive valid data, the SSPBUF should be read before

the next byte of data to transfer is written to the

SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates

when SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

bit BF is cleared. This data may be irrelevant if the SPI

is only a transmitter. Generally the SSP Interrupt is

used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or writ-

ten. If the interrupt method is not going to be used, then

software polling can be done to ensure that a write col-

lision does not occur. Example 11-2 shows the loading

of the SSPBUF (SSPSR) for data transmission. The

shaded instruction is only required if the received data

is meaningful.

EXAMPLE 11-2: LOADING THE SSPBUF

(SSPSR) REGISTER

(PIC16C66/67)

BCF

STATUS, RP1

;Specify Bank 1

BSF

STATUS, RP0

;

LOOP BTFSS SSPSTAT, BF

;Has data been

;received

;(transmit

;complete)?

GOTO

LOOP

;No

BCF

STATUS, RP0

;Specify Bank 0

MOVF

SSPBUF, W

;W reg = contents

; of SSPBUF

MOVF

TXDATA, W

;W reg = contents

; of TXDATA

MOVWF SSPBUF

;New data to xmit

The block diagram of the SSP module, when in SPI

mode (Figure 11-9), shows that the SSPSR is not

directly readable or writable, and can only be accessed

from addressing the SSPBUF register. Additionally, the

SSP status register (SSPSTAT) indicates the various

status conditions.

FIGURE 11-9: SSP BLOCK DIAGRAM

(SPI MODE)(PIC16C66/67)

MOVWF RXDATA

;Save in user RAM

Read

Write

Internal

data bus

RC4/SDI/SDA

RC5/SDO

RA5/SS

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TCY

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

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